Planar Electronic Device Multi-Height Imprint Patterning
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Solution Overview
Problem
The manufacturing of planar electronic devices faces challenges in aligning multiple masks or tools, achieving small feature sizes on the nanoscale, and producing devices with high conductivity terminals while maintaining efficiency and compatibility with large-area production.
Innovation Solution
A method where the positions of terminals, semiconductor channels, and dielectric material are defined by a single patterning step using a multi-height imprint tool, allowing for efficient alignment and enhanced conductivity through subsequent processing, enabling the production of planar electronic devices with large terminal regions suitable for high-density interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks or patterned tools are used in the manufacturing process, then device features can be defined with precision, but alignment between successive masks becomes difficult and increases process complexity
Solution Approach 1:
The patent segments the patterning process into two distinct functions: a first patterning step defines terminal positions using a first mask, and a second patterning step defines channel positions using a second mask. This segmentation allows each mask to be optimized for its specific function and simplifies the alignment requirements compared to using a single complex mask for all features.
Solution Approach 2:
The first mask is used in advance to define terminal positions and form terminal contacts before the second patterning step. This preliminary action establishes reference points that guide subsequent processing steps, including the alignment of the second mask, thereby reducing the complexity of later alignment operations.
2Device complexity
If semiconductor material is used for terminals, then device structure is simplified, but terminal conductivity is relatively low which limits device speed and efficiency
Solution Approach 1:
The patent employs composite material structures for terminals, combining semiconductor material with highly conductive materials such as metals or metal alloys. This composite approach maintains the structural integration benefits of semiconductor terminals while dramatically improving electrical conductivity to enable high-speed device operation.
Solution Approach 2:
The patent applies different material properties to different regions of the terminal structure. The terminal contacts have high conductivity material for electrical connection, while the terminal regions integrated with the semiconductor channel maintain semiconductor properties for device control. This local differentiation optimizes both conductivity and structural function.
3Ease of operation
If terminal area is increased to facilitate connections, then interconnection ease is improved, but device area increases which conflicts with miniaturization requirements
Solution Approach 1:
The patent uses thin film structures for terminal contacts, allowing large-area electrical connections to be achieved with minimal vertical thickness. These thin film terminals can extend laterally to provide adequate connection area while maintaining a compact overall device footprint through the thin-film architecture.
Solution Approach 2:
The patent resolves the area conflict by transitioning to three-dimensional terminal structures, such as raised terminal regions or vertically stacked contact structures. This allows connection area to be increased in the vertical dimension or through lateral extension in controlled regions without proportionally increasing the planar device area, thereby maintaining miniaturization while facilitating interconnections.
Data Source
Figure 1a~1d
Figure 1e
Figure 2a~2c
AI summary
A method of manufacturing a substantially planar electronic device comprises: providing a substrate supporting a layer of semiconductor material; forming a layer of resist material over the semiconductor layer, the resist layer comprising a plurality of first portions having a first thickness, a second portion having a second thickness, and a plurality of third portions having a third thickness, wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness, the first portions defining positions of insulative features to be formed to interrupt the semiconductor layer and define at least a position of a semiconductor channel, the second portion covering at least the semiconductor channel, and the third portions defining positions of first and second terminals; processing the resist layer to remove the first portions, without removing entirely the second or third portions, to expose surfaces of corresponding underlying first portions of the semiconductor layer; removing the first portions of the semiconductor layer to expose surfaces of corresponding underlying first portions of the substrate and so form a plurality of insulative features interrupting the semiconductor layer and defining the position of the semiconductor channel; further processing the resist layer to remove the second portion of the resist layer, without removing entirely the third portions, to expose at least a surface of a second portion of the semiconductor layer, said second portion of the semiconductor layer providing the channel; depositing dielectric material on the resultant structure such that dielectric material fills the insulative features and forms a dielectric layer covering at least the semiconductor channel; and removing the remaining material of the third portions of the resist layer to expose surfaces of corresponding underlying third portions of the semiconductor layer.