Embedded Interconnects Planar Surface Substrate Design
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Solution Overview
Problem
The existing design of high-density embedded interconnects in substrates for integrated devices faces issues such as weak joints due to filler material flow into recessed interconnects and limited line and spacing dimensions, leading to peeling and lift-off problems as dimensions decrease.
Innovation Solution
The implementation of embedded interconnects that are partially located within and partially external to the dielectric layer, allowing for a planar surface configuration with a first portion embedded and a second portion exposed, reducing filler material interference and enabling finer pitch and spacing without peeling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded interconnects are recessed in the dielectric layer, then the interconnects are fully embedded, but filler material flows into the recess causing weak joints and open joints
Solution Approach 1:
The patent extracts the embedded interconnects from the recessed configuration and positions them on a planar surface of the dielectric layer. This removes the harmful recess geometry that causes filler material to flow in and creates weak joints, while maintaining the embedded nature of the interconnects within the dielectric structure.
Solution Approach 2:
Instead of recessing the interconnects below the dielectric surface, the patent inverts the approach by having the interconnects terminate at the planar surface. This inversion eliminates the recess problem while still achieving embedded interconnect functionality.
2Productivity
If line and spacing dimensions are reduced, then higher density interconnects are achieved, but peeling and lift off issues occur
Solution Approach 1:
The patent applies different geometries to different parts of the interconnect structure. The interconnects have a planar surface configuration at the dielectric interface rather than being recessed, which provides better mechanical support and prevents peeling at small dimensions while maintaining high density.
Solution Approach 2:
The patent changes the dimensional configuration of the interconnects from recessed (negative dimension relative to surface) to planar (zero dimension, flush with surface). This dimensional change eliminates the peeling and lift-off problems that occur at small line and spacing dimensions while maintaining high interconnect density.
Data Source
AI summary
A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.