Planar to FinFET Design Conversion with Timing Closure
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Solution Overview
Problem
The complexity and high costs associated with FinFET design processes, particularly in migrating from planar designs to timing-closed FinFET designs, pose significant challenges in achieving cost-effective and efficient performance.
Innovation Solution
A method and apparatus that convert planar designs into timing-closed FinFET designs by generating initial FinFET designs based on planar cells and a FinFET model, processing these designs to resolve race conditions and hold violations through delay adjustments, and utilizing a fin-based grid to select and modify FinFET cells, thereby reducing design and mask costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional FinFET design process is used, then performance and leakage characteristics are improved, but design complexity and mask costs increase significantly
Solution Approach 1:
The patent creates a simplified copy of the FinFET design process by taking existing planar designs and generating corresponding FinFET designs through automated conversion. This copying approach allows retention of proven planar design workflows while obtaining FinFET performance benefits, thereby reducing design complexity and mask costs compared to creating FinFET designs from scratch.
Solution Approach 2:
The patent transforms planar transistor designs into FinFET designs by changing key geometric parameters - specifically adding vertical fin structures to horizontal planar transistors. This parameter transformation enables the same logical design to achieve FinFET performance characteristics while maintaining compatibility with existing planar design flows, thus reducing overall design complexity.
2Use of energy by moving object
If planar designs are converted to FinFET designs, then power performance is improved, but timing closure becomes more difficult to achieve
Solution Approach 1:
The patent implements timing analysis and timing closure techniques in the automated conversion process. By feeding back timing information from the generated FinFET design and adjusting the conversion parameters accordingly, the system achieves timing closure while maintaining the power performance benefits of FinFET structures.
Solution Approach 2:
The patent makes the FinFET design generation process dynamic by allowing adjustment of fin height, width, and other parameters based on timing requirements. This dynamic adjustment enables the system to optimize both power performance and timing characteristics, resolving the contradiction between improved power performance and difficult timing closure.
3Loss of energy
If FinFET structures are implemented, then leakage is reduced, but design and mask costs increase
Solution Approach 1:
The patent copies existing planar designs and automatically converts them to FinFET implementations, avoiding the need to create new FinFET designs from scratch. This copying approach reduces design and mask costs while still achieving the leakage reduction benefits of FinFET structures, as the conversion process reuses proven design elements.
Solution Approach 2:
The patent performs preliminary actions by pre-processing planar designs and preparing FinFET conversion templates before actual manufacturing. This preliminary preparation simplifies the overall manufacturing process and reduces costs associated with creating new FinFET designs, while maintaining the leakage reduction advantages.
Data Source
AI summary
An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.