Planar FinFET Gate Formation for Precise Metal Gate Replacement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and cost.
Innovation Solution
A method for forming a semiconductor device structure involves creating fin structures on a substrate, forming isolation layers, dummy gates, and spacers, followed by ion implantation to create heavily doped regions, and then replacing dummy gates with a gate dielectric and metal gate electrode, using a planarization layer to ensure uniformity and precision in gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential steps including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation of the complex fabrication process into manageable stages enables precise control at each step, making it feasible to manufacture devices at smaller feature sizes while maintaining production efficiency
Solution Approach 2:
Dummy gates are formed in advance before the actual gate structure is created. These preliminary dummy gates serve as templates and protection layers during subsequent fabrication steps, including spacer formation and material deposition. This preliminary action simplifies the overall process by providing a reference structure that guides subsequent steps, reducing complexity in forming the final gate structure at scaled dimensions
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Spacer structures are introduced as intermediary elements between the mandrels and the final gate structure. The spacers provide a controlled, uniform thickness layer that defines the gate dimensions with high precision. This intermediary approach allows precise control of gate width and positioning at scaled dimensions without directly patterning the gate material, thereby maintaining manufacturing precision while reducing chip area
Solution Approach 2:
The fabrication process utilizes controlled changes in material properties and deposition parameters to achieve precise feature dimensions. By adjusting deposition thickness, etch selectivity, and removal conditions, the process maintains tight dimensional control at smaller feature sizes, ensuring high manufacturing precision despite reduced chip area
3Reliability
If dummy gates are replaced with metal gate electrodes, then device performance is improved, but process complexity increases
Solution Approach 1:
The gate structure is formed with different materials and properties in different regions. Metal gate electrodes are selectively formed in specific areas where high performance is required, while other regions may retain different structures. This local differentiation improves device reliability in critical areas without unnecessarily complicating the entire gate structure across the chip
Solution Approach 2:
The dummy gate structures are selectively removed after serving their purpose as templates during fabrication. The removal process recovers the underlying channel regions for final gate formation. This discarding of temporary structures simplifies the final gate structure complexity while maintaining the benefits of the dummy gate approach during manufacturing, thereby improving device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the uniformity and yield of semiconductor device structures by ensuring precise gate formation and uniformity over fin structures, enhancing the reliability and efficiency of semiconductor device manufacturing at smaller scales.
Implementation Method 1
performing a plasma deposition process to form a planarization layer over the gate material layer
Implementation Method 2
performing an etching process to remove the planarization layer and a first upper portion of the gate material layer so as to form a gate in the trench
Implementation Method 3
ion implantation to create heavily doped regions
Data Source
AI summary
A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The device includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.