Planar to FinFET Design Conversion via Grid Superimposition
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Solution Overview
Problem
Current methods for converting planar integrated circuit designs to FinFET designs are resource-intensive and difficult to verify, especially at the reticle level, requiring significant computational resources and time for data processing.
Innovation Solution
A method that converts planar designs to FinFET designs by superimposing a FinFET design grid over a planar integrated circuit design, generating fin mandrels along specific grid lines, and removing them from outside areas, allowing for verification at the macro cell level and reducing data processing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conversion is performed at the reticle level, then complete design conversion is achieved, but verification becomes difficult and computational resources increase significantly
Solution Approach 1:
The patent divides the reticle-level conversion process into macro cell-level conversions. Each macro cell is converted independently from planar to FinFET design, allowing verification to be performed at the macro cell level rather than requiring processing of entire reticle data. This segmentation reduces computational complexity while maintaining verification capability.
2Manufacturing precision
If manual conversion from planar to FinFET layout is performed, then design conversion is achieved, but resource consumption in computation and human capital increases dramatically
Solution Approach 1:
The patent implements an automated conversion process where the system performs the planar-to-FinFET layout transformation itself through algorithmic operations. The process automatically identifies macro cells, generates FinFET layouts, and produces output data without requiring manual human intervention for each conversion step, thereby dramatically improving productivity while maintaining precision.
3Reliability
If product conversion includes changes to semiconductor layers above transistor level, then complete FinFET conversion is achieved, but many new photomasks must be created increasing fabrication cost
Solution Approach 1:
The patent performs conversion at the macro cell level rather than requiring complete reticle-level conversion. This partial action approach converts sufficient portions of the design to achieve FinFET functionality while avoiding the need to regenerate all upper semiconductor layers and associated photomasks, thereby reducing fabrication costs while maintaining conversion completeness for the critical transistor level.
Data Source
AI summary
Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits are provided. In one embodiment, a method for converting a planar integrated circuit design to a non-planar integrated circuit design includes identifying a rectangular silicon active area in the planar integrated circuit design, superimposing a FinFET design grid comprising a plurality of equidistantly-spaced parallel grid lines over the rectangular silicon active area such that two sides of the rectangular silicon active area are parallel to the grid lines, and generating a rectangular active silicon marker area encompassing the silicon active area. Furthermore, the method includes generating fin mandrels longitudinally along every other grid line of the plurality of grid lines and within the active silicon marker area and the silicon active area, and removing the fin mandrels from areas of the design grid outside of the active silicon marker area.