Planar to FinFET Design Conversion Grid Snapping
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Solution Overview
Problem
The complexity and high costs associated with developing FinFET designs, particularly in advanced technology nodes, necessitate a cost-effective method for converting planar designs into FinFET designs.
Innovation Solution
A method involving the receipt of a planar design with diffusion regions, overlapping parallel fin mandrels with a grid, snapping and cropping diffusion regions to align with grid lines, and generating a FinFET design by removing or replacing diffusion regions and adding dummy fill diffusion regions, while utilizing exclusion and keep-away regions to optimize the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET design is implemented directly without conversion from planar design, then device performance and leakage control are improved, but design complexity and development costs increase significantly
Solution Approach 1:
The patent applies copying by taking an existing planar design layout and creating a FinFET design copy through automated conversion processes. The planar design serves as a template that is transformed into FinFET structures, allowing the benefits of FinFET (lower leakage) to be achieved without manually designing from scratch, thus reducing design complexity while maintaining reliability improvements
Solution Approach 2:
The conversion process involves parameter changes by transforming 2D planar geometry parameters into 3D FinFET structure parameters. The automated system adjusts critical dimensions, fin heights, and material compositions during conversion, enabling the design to adapt to FinFET manufacturing requirements while maintaining electrical performance characteristics
2Power
If FinFET design is implemented in advanced technology nodes, then device performance is improved, but mask and development costs increase astronomically
Solution Approach 1:
By copying and adapting existing planar designs rather than creating new FinFET designs from scratch, the patent reduces the astronomical mask and development costs associated with advanced technology nodes. The automated conversion process reuses proven planar design layouts, minimizing the need for expensive new mask sets and validation cycles
Solution Approach 2:
The patent applies preliminary action by performing automated design conversion before the expensive mask fabrication and physical implementation stages. The conversion process prepares the design data in advance, identifying necessary modifications and optimizations, thereby reducing costs associated with late-stage design changes and rework
3Manufacturing precision
If manual FinFET design process is used, then design precision can be maintained, but conversion time and productivity are reduced
Solution Approach 1:
The patent replaces the manual mechanical design process with an automated computer-based conversion system. The automated tooling uses algorithms and computational methods to transform planar designs into FinFET designs, maintaining precision through systematic rule-based transformations while dramatically increasing conversion speed and productivity compared to manual processes
Data Source
AI summary
An approach for providing conversion of a planar design to a FinFET design is disclosed. Embodiments include: receiving a planar design having a plurality of diffusion regions; overlapping a plurality of parallel fin mandrels with a plurality of evenly-spaced parallel lines of a grid; snapping the diffusion regions to the grid based on the parallel lines; and generating a FinFET design based on the overlapping and the snapping. Embodiments include the parallel lines and the parallel fin mandrels being perpendicular to a poly orientation associated with the planar design, and determining a spacing length between the parallel lines; determining a plurality of edges of the diffusion regions that are parallel to the poly orientation; and cropping the diffusion regions until each of the edges has a length that is a multiple of the spacing length.