Automated Planar to FinFET Layout Conversion
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Solution Overview
Problem
The conversion of planar structure layouts to FinFET structure layouts is resource-intensive and costly due to the need for numerous new photomasks and redesign of semiconductor layers, particularly for existing products, as different design rules apply to planar and FinFET layouts.
Innovation Solution
A method is developed to automatically convert planar structure layouts to FinFET layouts by analyzing and matching planar active areas with FinFET active areas, generating mandrels, and optimizing FinFET active areas to minimize the number of new photomasks required, while maintaining electrical properties and design rule compliance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If planar structure layouts are manually converted to FinFET layouts by hand, then design conversion is achieved, but resource intensity and time consumption increase dramatically
Solution Approach 1:
The patent replaces manual mechanical layout conversion with an automated computer-based system that uses algorithms to transform planar layouts into FinFET layouts. The system automatically identifies planar active areas, generates corresponding FinFET active areas, and creates mandrel patterns without human intervention, thereby resolving the contradiction between conversion capability and conversion efficiency.
Solution Approach 2:
The conversion system performs self-service by automatically analyzing the input planar layout, determining appropriate FinFET parameters based on design rules, generating the transformed layout, and outputting results without requiring manual operation. This automation eliminates the resource-intensive manual process while maintaining design conversion capability.
2Ease of manufacture
If numerous new photomasks are created for layer changes, then FinFET manufacturing is achieved, but manufacturing cost increases dramatically
Solution Approach 1:
The patent makes existing photomasks multi-functional by designing the FinFET layout transformation to maintain compatibility with existing upper-layer photomasks. The automated system preserves layer alignment and design rules so that previously created photomasks can be reused for FinFET manufacturing, reducing the quantity needed while maintaining manufacturing capability.
Solution Approach 2:
The system changes only the necessary parameters at the transistor level (active area geometry, mandrel patterns) while keeping upper-layer parameters unchanged. This selective parameter modification allows existing photomasks to remain valid, reducing the number of new photomasks required from many to potentially just one or none.
3Manufacturing precision
If design rules for planar and FinFET layouts are applied separately, then layout accuracy is maintained, but conversion complexity increases
Solution Approach 1:
The patent incorporates FinFET design rules into the layout transformation algorithm in advance. The system is pre-programmed with the knowledge of how to translate planar design rules into equivalent FinFET design rules, allowing automatic compliance with both sets of rules during the conversion process without adding manual complexity.
Data Source
AI summary
A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.