Planar Floating Gate Formation via Sacrificial Mask
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Solution Overview
Problem
The manufacturing process of non-volatile memory cell structures often results in sharp corners and indentations on floating gates, leading to local electric field concentration and reliability issues such as power leakage and data interpretation errors due to the higher top surfaces of isolation structures.
Innovation Solution
A method involving the formation of strip-shaped conductive structures by creating a sacrificial layer between isolation structures, using it as a mask to shape the conductive layers, and patterning them to fill trenches, resulting in planar floating gates and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the typical manufacturing process of logic circuit structure is used to integrate non-volatile memory cell structure and logic circuit structure, then the manufacturing process integration is achieved, but the top surfaces of isolation structures become higher than the top surface of substrate, causing sharp corners and indentations on floating gates
Solution Approach 1:
A planarization layer is formed on the substrate before forming the floating gates. This preliminary action creates a flat surface that compensates for the height difference caused by the isolation structures, preventing sharp corners and indentations on the floating gates while maintaining manufacturing process integration
2Reliability
If the top surfaces of isolation structures are higher than the top surface of substrate, then the isolation structures provide proper electrical isolation, but local electric field concentration occurs at sharp corners and indentations of floating gates
Solution Approach 1:
The planarization layer is formed in advance to provide a flat surface for floating gate formation, eliminating the geometric irregularities that cause electric field concentration while preserving the electrical isolation function of the isolation structures
3Ease of manufacture
If sharp corners and indentations are present on floating gates, then the manufacturing process is simpler, but power leakage and data interpretation errors occur during programming and erasing steps
Solution Approach 1:
By forming the planarization layer before the floating gates, the method maintains manufacturing simplicity while ensuring that the floating gates have uniform shapes without sharp corners or indentations, thereby preventing power leakage and data errors during memory operations
Data Source
AI summary
A manufacturing method of floating gate is disclosed. A substrate having a plurality of isolation structures is provided, and top surfaces of the isolation structures are higher than a top surface of the substrate. A first conductive layer is formed on the substrate. A sacrificial layer is formed on the first conductive layer. Parts of the sacrificial layer are removed while parts of the sacrificial layer on the first conductive layer between the isolation structures are remained. Parts of the first conductive layer are removed by using the remaining parts of the sacrificial layer as masks to form conductive structures between the adjacent isolation structures. The remaining parts of the sacrificial layer are removed. A second conductive layer is formed on the substrate and the second conductive layer electrically connects with the conductive structures. The second conductive layer and the conductive structures are patterned to form floating gates.