Planar Fuse Structure for High-Frequency Circuits
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Solution Overview
Problem
Conventional fuse structures in semiconductor devices are not suitable for ultra-high-frequency circuits due to increased resistance and parasitic capacitance, which limits their performance and capability, especially when used in high-frequency applications like 77 GHz oscillators.
Innovation Solution
A fuse structure with a substrate, a fuse conductive trace closer to one chip surface, a metallization layer on the substrate, and a planar barrier multilayer assembly of different materials between the fuse conductive trace and the metallization layer, allowing for electrical isolation upon cutting, reducing resistance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deeply buried polysilicon lines are used to contact the fuse conductive trace, then corrosion propagation is limited, but resistance increases by tens of Ohms and parasitic capacitances increase
Solution Approach 1:
The patent transitions from vertical contact (deeply buried polysilicon lines extending vertically through the substrate) to planar contact (metallization layer arranged in the same plane as the fuse conductive trace). This dimensional change eliminates the need for vertical vias and deeply buried contacts, thereby reducing resistance and parasitic capacitance while maintaining corrosion protection through the planar barrier assembly.
Solution Approach 2:
The patent employs a composite barrier multilayer assembly consisting of multiple layers with different materials (e.g., tungsten, tungsten nitride, tantalum, tantalum nitride) to provide both corrosion protection and low resistance. The combination of different materials allows optimization of both protective and conductive properties, resolving the contradiction between corrosion protection and electrical performance.
2Ease of manufacture
If conventional fuse structures are used, then manufacturing is simple, but they are not suitable for ultra-high-frequency circuits due to increased resistance and parasitic capacitance
Solution Approach 1:
The patent maintains ease of manufacture by using standard planar fabrication processes while achieving ultra-high-frequency performance through the planar configuration. The metallization layer is formed in the same plane as the fuse conductive trace using conventional photolithography and metallization deposition, eliminating complex vertical via structures while preserving manufacturing simplicity.
Solution Approach 2:
The patent changes the electrical parameters (resistance and parasitic capacitance) by altering the geometric configuration from vertical to planar. This parameter change enables the fuse structure to meet the stringent requirements of ultra-high-frequency circuits while maintaining compatibility with standard manufacturing processes.
3Reliability
If vertical conductors and vias are used to create electrical connection, then corrosion is contained, but resistance increases by tens of Ohms
Solution Approach 1:
The patent eliminates vertical conductors and vias by arranging the metallization layer in the same plane as the fuse conductive trace. This planar configuration removes the vertical path that causes high resistance, while corrosion containment is maintained through the planar barrier multilayer assembly that prevents lateral corrosion propagation.
Solution Approach 2:
The patent introduces a planar barrier multilayer assembly as an intermediary between the fuse conductive trace and the metallization layer. This barrier assembly provides corrosion protection without requiring deeply buried polysilicon lines, thereby maintaining low resistance while preventing corrosion propagation.
Data Source
AI summary
A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.