Planar Gate Stack Test Structure Without Body Isolation
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Solution Overview
Problem
Body isolation processes in semiconductor device manufacture often result in inconsistent body isolation layers, making it challenging to accurately test the thickness of gate oxide due to unclear resistance contributions from the body isolation and gate dielectric layers.
Innovation Solution
A method involving the formation of a planar semiconductor device without a body isolation dielectric layer, where a stack of semiconductor layers is supported by a dielectric fin, allowing for consistent deposition of a gate dielectric layer and subsequent conductive material, enabling precise measurement of gate dielectric thickness by applying voltage and measuring current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a body isolation dielectric layer is formed in the semiconductor device, then device isolation is achieved, but the gate oxide thickness measurement becomes inaccurate due to inconsistent dielectric layer thickness
Solution Approach 1:
The device is segmented into two functional regions: a first region with body isolation for device isolation and a second region without body isolation for accurate gate oxide thickness measurement. This segmentation allows each region to serve its specific purpose without interfering with the other's performance
Solution Approach 2:
The patent creates a test structure that copies the gate stack configuration from the main device but omits the body isolation layer, allowing the gate oxide thickness to be measured in isolation without the confounding factor of inconsistent body isolation dielectric thickness
2Ease of manufacture
If body isolation processes are used to form devices, then device separation is achieved, but testing gate oxide thickness becomes challenging due to unclear resistance contributions
Solution Approach 1:
The body isolation dielectric layer is selectively removed or excluded from the test structure, extracting the gate stack from the body isolation context. This allows the gate oxide thickness to be measured independently without the resistance contribution from the body isolation dielectric
Solution Approach 2:
A dedicated test structure serves as an intermediary between the body isolation device and the measurement process. This test structure provides a clean measurement path that isolates the gate oxide resistance from other parasitic resistances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate determination of gate dielectric thickness, distinguishing it from the body isolation dielectric layer's resistance, thereby improving the reliability of gate oxide thickness testing in semiconductor devices.
Implementation Method 1
A dielectric layer is conformally deposited on the exposed substrate surface. The dielectric layer has a consistent thickness across the top surface.
Implementation Method 2
A conductive material is deposited over the dielectric layer.
Implementation Method 3
enabling precise measurement of gate dielectric thickness by applying voltage and measuring current
Data Source
AI summary
Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.