Planar III-N Semiconductor Layer via Nanostructure Coalescence
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Solution Overview
Problem
The challenge in fabricating high-quality III-nitride semiconductor wafers lies in the inability to achieve epitaxial growth close to thermal equilibrium, particularly due to the difficulty in creating and maintaining a congruent GaN melt, leading to high dislocation densities and increased costs associated with using foreign substrates like SiC and Sapphire.
Innovation Solution
A method involving the growth of III-N semiconductor layers on a substrate with a buffer layer and a mask layer, where nanostructures are formed and coalesced at elevated temperatures to create a planar, dislocation-free layer, utilizing a nitrogen-rich environment and controlled atomic redistribution to minimize dislocations and achieve thermal expansion mismatch for lattice alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If mismatched growth on foreign substrates (SiC, Sapphire, Si) is used to fabricate III-nitride semiconductors, then the production cost is reduced and manufacturing is enabled, but high densities of crystal dislocations are generated
Solution Approach 1:
The substrate surface is segmented into multiple nanosized apertures arranged in an array, allowing epitaxial growth to occur in discrete regions. This segmentation enables controlled growth of nanostructures that can be subsequently coalesced, addressing the dislocation problem while maintaining manufacturability through patterned growth zones.
Solution Approach 2:
A mask layer with nanosized apertures is introduced as an intermediary between the substrate and the epitaxial growth process. This intermediary structure controls where growth occurs, enabling the formation of dislocation-free nanostructures that can be coalesced into a continuous layer, thus improving crystal quality without sacrificing manufacturability.
2Productivity
If conventional epitaxial growth methods are used, then continuous crystal growth is achieved, but threading dislocations propagate through the grown layers
Solution Approach 1:
The continuous growth process is divided into discrete epitaxial growth regions defined by the nanosized apertures in the mask layer. Each aperture acts as an independent growth zone, allowing continuous material deposition while preventing dislocation propagation between zones. The segmented approach maintains productivity through continuous growth while improving precision by isolating dislocation sources.
Solution Approach 2:
Threading dislocations are extracted or removed from the growth process by using the mask layer to block dislocation propagation. The nanosized apertures prevent dislocations from traveling between growth regions, effectively taking out the harmful dislocation component while maintaining continuous crystal growth in each isolated zone.
3Ease of manufacture
If foreign substrates are used for III-nitride growth, then the fabrication process becomes feasible, but thermal expansion mismatch causes lattice misalignment
Solution Approach 1:
The substrate surface is divided into discrete growth regions through the mask layer with nanosized apertures. This segmentation allows each region to be grown and then coalesced, enabling better control over lattice alignment while maintaining fabrication feasibility on foreign substrates. The segmented approach isolates thermal mismatch effects to local regions.
Solution Approach 2:
The growth process utilizes elevated temperatures to facilitate coalescence of nanostructures into a continuous layer. By changing the temperature parameter during different growth stages, the process accommodates thermal expansion mismatch while achieving the desired lattice alignment in the final coalesced structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a dislocation-free, planar III-N semiconductor layer with reduced threading dislocations, enabling the production of high-quality III-nitride wafers with improved material quality and reduced production costs by eliminating the need for foreign substrates.
Implementation Method 1
epitaxially growing a III-N material in the apertures to form nanostructures
Implementation Method 2
epitaxial growth is largely limited and governed by the diffusion of source material to the crystal surface
Implementation Method 3
coalescing upper parts of the nanostructures at an elevated temperature T to form a continuous planar layer
Implementation Method 4
controlled atomic redistribution to minimize dislocations and achieve thermal expansion mismatch for lattice alignment
Implementation Method 5
the growth layer is configured such that thermal expansion between RT and T of the growth layer is greater than thermal expansion of the substrate
Implementation Method 6
thermal expansion mismatch for lattice alignment
Data Source
AI summary
A semiconductor device having a planar III-N semiconductor layer includes a substrate including a wafer and a buffer layer of a buffer material different from a material of the wafer, the buffer layer having a growth surface, an array of nanostructures epitaxially grown from the growth surface, a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T, where the number of lattice cells spanning a center distance between adjacent nanostructures are different at the growth surface and at the coalesced planar layer, and a growth layer epitaxially grown on the planar layer.