Planar Inductor with Overlapping Terminals for Integrated Capacitance
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Solution Overview
Problem
In semiconductor chip design, the integration of filters with inductors and capacitors in parallel connection is limited by the larger area occupied by inductors, requiring additional connection lines that increase the filter's area and introduce unnecessary coupling effects, making it challenging to reduce the design area and improve communication quality.
Innovation Solution
A circuit device with a planar inductor embedded in an insulating material layer, featuring overlapping connection terminals and a capacitor dielectric layer within the overlapping region, which forms a capacitor without the need for additional connection lines, allowing for a more compact design by utilizing the overlapping area for capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional connection lines are used to connect the capacitor and inductor in parallel connection, then the circuit functionality is achieved, but the filter area increases and communication quality deteriorates due to coupling effects
Solution Approach 1:
The patent merges the capacitor structure with the connection terminals of the planar inductor by positioning the capacitor directly over the overlapping region of the inductor's connection terminals. This integration eliminates the need for separate connection lines between the capacitor and inductor, thereby reducing the filter area and minimizing parasitic coupling effects that would degrade communication quality.
Solution Approach 2:
The connection terminals of the planar inductor serve dual functions: they act as connection points for the inductor and simultaneously as one of the electrodes for the capacitor. This multi-functionality reduces the number of additional connection lines required, decreasing both the filter area and the parasitic inductance that would otherwise affect signal integrity and communication quality.
2Area of stationary object
If the inductor area is reduced to fit more components on the chip, then the chip area utilization improves, but the inductor performance deteriorates due to smaller effective area
Solution Approach 1:
The patent utilizes the vertical dimension by positioning the capacitor in the third dimension (overlapping region) rather than placing it in the same planar space as the inductor. This three-dimensional integration allows the inductor to maintain its full effective area for optimal performance while the capacitor occupies the vertical space above the inductor's connection terminals, improving chip area utilization without compromising inductor performance.
3Adaptability or versatility
If transmission lines are used to connect independent inductors and capacitors, then the circuit design flexibility is maintained, but the connection line effects increase and design area expands
Solution Approach 1:
The patent combines the capacitor structure with the inductor's connection terminals, eliminating the need for separate transmission lines. The capacitor is positioned directly over the overlapping region of the inductor terminals, creating an integrated structure that maintains circuit functionality while removing the parasitic effects and area overhead associated with additional connection lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the required connection lines and area occupied by the filter, enhancing chip design efficiency and communication quality by effectively integrating inductors and capacitors in parallel connection within the semiconductor chip.
Implementation Method 1
A capacitor dielectric layer is located within the overlapping region between the first connection terminal and the second connection terminal, and the capacitor dielectric layer, the first connection terminal and the second connection terminal together form a capacitor
Data Source
AI summary
A circuit device having an inductor and a capacitor in parallel connection includes a planar inductor embedded in an insulating material layer, wherein the planar inductor has a winding wire portion, a first connection terminal and a second connection terminal. The first connection terminal and the second connection terminal are located at different elevations and have an overlapping region. A capacitor dielectric layer is located within the overlapping region between the first connection terminal and the second connection terminal, and the capacitor dielectric layer and the first connection terminal and the second connection terminal together form a capacitor.