Planar Interconnection Layer for Optoelectronic Semiconductor Chips
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Solution Overview
Problem
Existing optoelectronic semiconductor chips face challenges in achieving a low-complexity structure that is also ageing-resistant, as complex insulation layers used for electrical contacting are prone to degradation and current leaks over time, leading to potential electrical short circuits.
Innovation Solution
The optoelectronic semiconductor chip incorporates a planar interconnection layer with a first and second electrically conductive contact layer and an insulation layer made of high-specific-resistance material, ensuring a seamless, planar mounting face that maintains stability and prevents electrical shorts, using materials like BCB, silicone resin, and sol-gel materials for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex insulation layers are used for electrical contacting, then electrical insulation is achieved, but the structure becomes prone to degradation and current leaks over time
Solution Approach 1:
The patent extracts the problematic complex insulation layer structure and replaces it with a simplified interconnection layer design. The complex multi-layer insulation structure is removed and substituted with a planar interconnection layer having a mounting face, which maintains electrical insulation functionality while eliminating the complexity that caused degradation and current leaks over time.
Solution Approach 2:
The patent changes the structural parameters of the insulation system by transitioning from a complex multi-layer vertical structure to a planar interconnection layer with a flat mounting face. This parameter change simplifies the structure while maintaining the electrical insulation function, thereby improving ageing resistance by eliminating complex interfaces that are prone to degradation.
2Reliability
If complex insulation layers are used for electrical contacting, then electrical insulation is achieved, but the structure becomes more complex
Solution Approach 1:
The patent merges the electrical insulation function with the interconnection layer structure itself. Instead of using separate complex insulation layers, the interconnection layer is designed with an integrated planar mounting face that provides both mechanical support and electrical insulation. This merging simplifies the overall structure while maintaining insulation stability.
Solution Approach 2:
The interconnection layer with its planar mounting face serves multiple functions simultaneously: it provides mechanical support for mounting optoelectronic semiconductor bodies, provides electrical insulation between conductive contact layers, and enables planar assembly. This multi-functionality eliminates the need for separate complex insulation structures.
3Reliability
If complex insulation layers are used, then electrical contacting is achieved, but current leaks and electrical short circuits occur over time
Solution Approach 1:
The patent applies preliminary anti-action by designing the interconnection layer with a planar mounting face that prevents the formation of defects from the outset. The simplified planar structure eliminates complex interfaces and stress concentration points that would otherwise lead to degradation, current leaks, and electrical shorts during operation, thereby maintaining insulation integrity over time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable and ageing-resistant optoelectronic semiconductor chip with reduced complexity in structure, minimizing the risk of electrical shorts and maintaining insulation integrity over extended operation periods.
Implementation Method 1
an insulation layer which is formed of an electrically insulating material... the insulation layer comprises an electrically insulating material which is capable of electrically insulating the first electrically conductive contact layer from the second electrically conductive contact layer
Data Source
AI summary
An optoelectronic semiconductor chip includes an interconnection layer with a first electrically conductive contact layer, a second electrically conductive contact layer and an insulation layer, which is formed of an electrically insulating material. Further, the optoelectronic semiconductor chip includes two optoelectronic semiconductor bodies, each of which include an active region that is intended to generate radiation. The insulation layer is arranged on a top of the second electrically conductive contact layer facing the optoelectronic semiconductor bodies. The first electrically conductive contact layer is arranged on a top of the insulation layer remote from the second electrically conductive contact layer. The optoelectronic semiconductor bodies are interconnected electrically in parallel by the interconnection layer.