Planar MOS Transistor Layout for Low-Noise RF Gate Control
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Solution Overview
Problem
Current transistor designs in low noise amplifiers, such as FinFET architecture, fail to achieve satisfactory performance due to insufficient parameters like gate resistance and gate to body capacitance, limiting the overall performance of wireless RF systems.
Innovation Solution
The method involves replacing FinFET transistors with planar NMOS and PMOS transistors and planar MOS capacitors, where the Q-value of planar transistors relies on gate structure widths and capacitance is determined by the overlapped area between the metal gate and doped region, improving gate density and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET architecture is used, then device integration is improved, but gate resistance and gate to body capacitance parameters are insufficient
Solution Approach 1:
The patent applies different transistor architectures to different functional regions: FinFET architecture is used in the core logic device region for high integration and performance, while planar transistor architecture is used in the low noise device region for optimized gate resistance and capacitance parameters. This local differentiation resolves the contradiction by allowing each region to have the quality it needs.
2Reliability
If planar transistors are used in low noise devices, then gate resistance and capacitance parameters are improved, but device integration density decreases
Solution Approach 1:
The semiconductor device is segmented into distinct functional regions: a core logic device region using FinFET architecture and a low noise device region using planar transistor architecture. This segmentation allows each region to be optimized independently - the core region maximizes integration density while the low noise region optimizes electrical parameters like gate resistance and capacitance.
3Area of stationary object
If FinFET architecture is used in low noise devices, then area efficiency is improved, but analog circuit performance is insufficient
Solution Approach 1:
The patent recognizes that different functional requirements demand different structural qualities. Low noise analog circuits require specific electrical characteristics (low gate resistance, controlled capacitance) that are best achieved with planar transistors, while digital logic benefits from the area efficiency of FinFETs. By assigning planar transistors specifically to the low noise device region, the patent optimizes analog circuit performance without compromising overall area efficiency.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.