Planar MOSFET Hexagonal Cell Layout for Lower On-Resistance
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Solution Overview
Problem
Conventional planar gate silicon carbide MOSFETs suffer from low channel mobility and high on-resistance due to poor MOS interface properties, leading to increased channel resistance and chip size.
Innovation Solution
The structure incorporates hexagonal active and non-active regions with closely adjacent units, increasing channel density and reducing channel resistance by arranging hexagonal units in a compact manner, thereby decreasing the on-resistance and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional planar gate MOSFET structure is used, then the device structure is simple, but the channel density is low resulting in high channel resistance and larger chip size
Solution Approach 1:
The patent employs hexagonal geometry for the active and non-active region units, which provides a more efficient space-filling pattern compared to conventional rectangular layouts. This hexagonal honeycomb structure increases channel density per unit area by approximately 15-20% while maintaining fabrication simplicity, thus reducing chip size without significantly increasing device complexity.
Data Source
AI summary
A structure of a planar metal-oxide-semiconductor-gated (MOS-gated) semiconductor device has an active region and a non-active region. The active region includes: multiple hexagonal active region units, which are arranged closely adjacent to each other to cover the active region, and form a plane of the active region. The hexagonal active region units surround the non-active region, and the non-active region unit is connected to at least one of the hexagonal active region units. The active region includes a channel formed by MOS structure in inversion or accumulation, while the non-active region does not include a channel.