Planar MOSFET SiGe Source/Drain Layout to Minimize STI Facets
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Solution Overview
Problem
Conventional CMOS processing techniques often result in silicon germanium facets forming near the bottom of recesses in shallow trench isolation regions, which can undermine the strain-inducing effects of silicon germanium source/drain regions, preventing full benefits from being realized due to incomplete growth and requiring excessive device space for dummy structures.
Innovation Solution
The method involves forming shallow trench isolation areas after the gate stacks and silicon germanium source/drain regions are fabricated, using dummy gate stacks to allow for epitaxial growth of silicon germanium without truncating existing source/drain regions, and then replacing these with functional gates and etching trenches for isolation, ensuring intact silicon germanium regions and preventing facet formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation areas are formed before silicon germanium source/drain regions, then isolation between transistors is achieved, but silicon germanium facets form near the bottom of recesses which undermines strain-inducing effects
Solution Approach 1:
The patent applies preliminary action by forming the silicon germanium source/drain regions before creating the shallow trench isolation areas. This sequence allows the silicon germanium to fully grow and establish its strain-inducing effects on the channel before the isolation trenches are etched, preventing facet formation that would occur if isolation were formed first.
Solution Approach 2:
The patent inverts the conventional fabrication sequence by reversing the order of operations: instead of forming isolation trenches first and then adding silicon germanium, the method forms silicon germanium source/drain regions first and then creates the shallow trench isolation areas, thereby eliminating the facet formation problem.
2Manufacturing precision
If dummy structures are used to prevent facet formation, then strain-inducing effects are maintained, but excessive device space is required
Solution Approach 1:
The patent extracts and eliminates the need for dummy structures by changing the fabrication sequence. By forming silicon germanium source/drain regions before shallow trench isolation, the method achieves complete silicon germanium growth without requiring additional dummy structures to prevent facet formation, thereby reducing device space requirements.
3Speed
If silicon germanium is grown epitaxially within recesses, then carrier mobility is increased, but incomplete growth occurs due to facet formation
Solution Approach 1:
The patent applies preliminary action by performing the silicon germanium epitaxial growth before etching the shallow trench isolation trenches. This ensures that the silicon germanium can grow completely within the source/drain regions without being truncated by subsequent trench formation, achieving full carrier mobility enhancement.
Solution Approach 2:
The patent inverts the conventional sequence by growing silicon germanium first and then forming isolation trenches, rather than forming trenches first and then growing silicon germanium. This reversal prevents facet formation and ensures complete growth, maximizing carrier mobility benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for fully formed silicon germanium source/drain regions to maintain strain-induced effects, enhancing transistor performance without the need for additional space-consuming dummy structures, thus improving device performance and efficiency.
Implementation Method 1
The silicon germanium is typically introduced as a stressor by growing the silicon germanium epitaxially within recesses in the source/drain (S/D) regions of the transistor
Data Source
AI summary
A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.