Planar Multi Semiconductor Chip Package With Through Electrodes
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Solution Overview
Problem
Conventional memory devices, such as DRAM, require long wires for data transfer with processors, increasing data processing time, power consumption, and system size due to the need for controllers, which hampers high-speed processing.
Innovation Solution
A planar multi semiconductor chip package is designed with a substrate and two semiconductor chips, where memory devices are arranged in an m×n matrix, with through electrodes connecting the processor chip directly to the memory chip and substrate, minimizing wire length and optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory devices and processors are connected via long wires on a system board, then system size is increased, but data processing speed decreases and power consumption increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. Memory devices and processors are arranged in vertical layers connected by through-electrodes, transforming the connection path from horizontal wires across a system board to vertical pathways through the stack. This dimensional change dramatically reduces the effective connection length while increasing spatial utilization.
Solution Approach 2:
The patent implements a nested structure where multiple memory devices are stacked around and between processor chips in a compact arrangement. The through-electrodes pass through multiple layers, creating a nested configuration where components are embedded within the vertical stack. This nesting allows multiple devices to share common connection pathways, reducing overall wire length and system footprint.
2Use of energy by stationary object
If memory devices and processors are connected via long wires, then system size increases, but power consumption increases
Solution Approach 1:
By stacking memory devices and processors in vertical layers and connecting them through through-electrodes, the patent reduces the horizontal wire length that would otherwise extend across a system board. This vertical arrangement minimizes the distance electrical signals must travel, thereby reducing resistive power losses and improving energy efficiency.
Solution Approach 2:
The patent merges multiple connection functions into shared through-electrodes that serve multiple devices simultaneously. Instead of having separate wire connections for each device pair, the through-electrodes are reused across multiple layers, reducing the total amount of conductive material needed and the associated power consumption.
3Length of stationary object
If memory devices are arranged in a compact stack, then wire length is minimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming through-holes through the substrate, depositing conductive materials to create through-electrodes, arranging memory devices in the desired stack configuration, and establishing interconnections. This segmentation allows each manufacturing step to be optimized independently, making the complex three-dimensional assembly more manageable despite its inherent complexity.
Data Source
AI summary
Provided are a planar multi semiconductor chip package in which a processor and a memory device are connected to each other via a through electrode and a method of manufacturing the planar multi semiconductor chip package. The planar multi semiconductor chip package includes: a substrate comprising a plurality of first circuit patterns on a first surface and a plurality of second circuit patterns on a second surface; a first semiconductor chip comprising a plurality of memory devices arranged on the substrate, wherein first memory devices surround at least a portion of second memory devices; a second semiconductor chip stacked on the first semiconductor chip and corresponding to the second memory devices; and a plurality of through electrodes arranged on the second memory devices and connecting the first and second semiconductor chips to the second circuit pattern of the substrate.