Planar NVM Dielectric Reduces Capacitance
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Solution Overview
Problem
In non-volatile memory (NVM) cells, the equilibrium between electron tunneling from the substrate to nanocrystals and from nanocrystals to the control gate limits erase efficiency and increases erase time, as electrons can tunnel from the substrate to nanocrystals counteracting the desired top-side tunneling, leading to no net loss of electrons.
Innovation Solution
A dielectric layer with a substantially planar interface between the control gate and nanocrystals, rather than a conformal one, is used, along with a thin thickness over nanocrystals to reduce capacitance, allowing for increased electron tunneling from nanocrystals to the control gate while minimizing tunneling from the substrate, achieved through high-temperature oxide deposition and chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conformal dielectric layer is used over nanocrystals, then the dielectric provides uniform coverage, but the capacitance between control gate and nanocrystals is increased, reducing electron tunneling efficiency
Solution Approach 1:
The dielectric layer is made thinner specifically over the nanocrystal regions while maintaining adequate coverage, creating local variation in thickness that reduces capacitance where it matters most (over the nanocrystals) while still providing dielectric coverage. This local quality change optimizes the balance between coverage and capacitance reduction.
Solution Approach 2:
The dielectric thickness parameter is changed from uniform (conformal) to non-uniform (thinner over nanocrystals), which directly reduces the capacitance between control gate and nanocrystals. This parameter change enables improved electron tunneling efficiency during erase operations.
2Productivity
If high voltage is applied to control gate for electron tunneling, then erasing performance is improved, but substrate-to-nanocrystal tunneling counteracts the effect, reaching equilibrium with no net electron loss
Solution Approach 1:
The electric field distribution is made non-uniform by the varied dielectric thickness, creating stronger field concentration over the nanocrystals where it is needed for efficient electron tunneling to the control gate, while the thinner dielectric region specifically enhances this local tunneling effect.
Solution Approach 2:
The problem of electron tunneling equilibrium is addressed by introducing a spatial dimension variation in dielectric thickness, creating preferential tunneling paths with lower capacitance regions that favor top-side tunneling over substrate-to-nanocrystal tunneling.
3Reliability
If dielectric thickness is reduced over nanocrystals, then electron tunneling efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric layer is deposited with predetermined thickness variation patterns that are designed to achieve the desired capacitance reduction while accounting for manufacturing capabilities. The thickness profile is pre-planned to balance performance goals with manufacturability.
Solution Approach 2:
The dielectric thickness parameter is optimized to a specific range that achieves sufficient capacitance reduction for improved tunneling efficiency while remaining within manufacturable tolerances. This parameter optimization resolves the contradiction between performance and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency of electron tunneling from nanocrystals to the control gate, reducing erase voltage and time, and increases the differential between the erased and programmed states, thereby improving erase performance.
Implementation Method 1
The result is reduced capacitance between the control gate and the nanocrystals for a given dielectric thickness directly over the nanocrystals
Implementation Method 2
both programming and erasing require significantly more time than reading. Thus, there is the continuing effort to reduce the voltages required for programming and erase and reduce the time for performing those functions. In the case of erasing, which is typically removing electrons from a storage layer. In the case of nanocrystals being used for the storage layer, this is achieved using tunneling
Implementation Method 3
achieved through high-temperature oxide deposition and chemical mechanical polishing
Implementation Method 4
achieved through high-temperature oxide deposition and chemical mechanical polishing
Data Source
AI summary
A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements. A control gate is on the top layer of oxide. A surface of the top layer of oxide facing a surface of the control gate is substantially planar.