Planar Oxide Semiconductor Transistor Parasitic Capacitance
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from signal delay due to parasitic capacitance, leading to degraded image quality, especially in high-resolution and large-screen displays, and occupy more space compared to planar transistors, necessitating a semiconductor device with stable semiconductor characteristics, high reliability, and a simple manufacturing process.
Innovation Solution
A planar-type semiconductor device with an oxide semiconductor film, featuring regions with different impurity element concentrations and a nitride insulating film, where the gate, source, and drain electrodes contain the same metal element, and the oxide semiconductor film includes a first region overlapped with the gate and a second region not overlapped, with the second region having a higher impurity element concentration or hydrogen concentration, to reduce parasitic capacitance and enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor is used, then the manufacturing process is simple and manufacturing cost is low, but signal delay increases due to parasitic capacitance and image quality degrades
Solution Approach 1:
The oxide semiconductor film is divided into multiple regions with different impurity concentrations: a first region with lower impurity concentration and a second region with higher impurity concentration. This segmentation allows different parts of the film to serve different functions - the first region provides stable semiconductor characteristics while the second region enhances conductivity and reduces parasitic capacitance, thereby resolving the contradiction between manufacturing simplicity and signal delay.
Solution Approach 2:
Different regions of the oxide semiconductor film are given different local properties through controlled impurity concentration variations. The first region maintains low impurity concentration for stability, while the second region has higher impurity concentration (or hydrogen concentration) to reduce parasitic capacitance. This local quality differentiation enables the transistor to achieve both ease of manufacture and reduced signal delay.
2Ease of manufacture
If an inverted staggered transistor is used, then manufacturing cost is low, but occupation area is larger than planar transistor
Solution Approach 1:
Instead of adopting the conventional planar transistor structure to reduce occupation area, the invention inverts the approach by using an inverted staggered transistor structure and compensating for its larger area through impurity concentration optimization. This inversion allows maintaining manufacturing simplicity and low cost while mitigating the area disadvantage through the multi-region impurity concentration design.
3Ease of manufacture
If oxide semiconductor film with uniform impurity concentration is used, then manufacturing is simple, but cannot simultaneously achieve high on-state current and low off-state current
Solution Approach 1:
The oxide semiconductor film is designed with non-uniform impurity concentration distribution, where the first region has lower impurity concentration for low off-state current and stable characteristics, while the second region has higher impurity concentration for high on-state current and reduced parasitic capacitance. This local quality differentiation resolves the contradiction between manufacturing simplicity and electrical characteristic stability.
Solution Approach 2:
The impurity concentration parameter is changed across different regions of the oxide semiconductor film. By controlling the impurity concentration to be lower in the first region and higher in the second region, the invention achieves both high on-state current and low off-state current, thereby improving electrical characteristic stability while maintaining reasonable manufacturing complexity.
Data Source
AI summary
A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations. The gate electrode, the source electrode, and the drain electrode contain the same metal element.