Planar IC Package Interconnects for Conductive Pillar Co-Planarity
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Solution Overview
Problem
The challenge in manufacturing smaller IC packages is the higher yield loss and difficulty in achieving co-planarity of conductive pillars, which affects chip attach precision and manufacturing yields.
Innovation Solution
The process involves creating conductive pillars on a substrate, covering them with a mold compound, grinding to expose the pillars, and attaching a die using conductive adhesive, all while ensuring the pillars are generally co-planar to within 5 um of each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If IC packages are made smaller to increase signal routing density, then more signal routing per unit area is achieved, but manufacturing precision deteriorates due to higher yield loss and difficulty in achieving co-planarity
Solution Approach 1:
The patent applies preliminary action by growing the conductive pillars to an initial height that exceeds the final required height, then performing a planarization process (grinding or chemical-mechanical polishing) to achieve the target co-planarity. This preliminary over-growth allows the subsequent planarization to effectively correct height variations and achieve the required precision within 5 um tolerance
Solution Approach 2:
The patent changes the physical state and dimensions of the conductive pillars through controlled growth and planarization processes. By adjusting the growth parameters to create taller pillars initially, then modifying their height through grinding or CMP, the system achieves the required co-planarity parameter (within 5 um variation) that enables finer pitch scaling
2Manufacturing precision
If conductive pillars are made taller to accommodate height variations, then co-planarity is improved, but manufacturing complexity increases due to additional grinding and planarization steps
Solution Approach 1:
The patent merges the conductive pillar growth with the molding compound formation process. The molding compound is applied over the conductive pillars, and both the compound and pillars are ground together in a single planarization step. This combining of operations reduces the total number of separate manufacturing steps while achieving the required co-planarity
3Area of moving object
If pitch is reduced to increase routing density, then signal routing per unit area is improved, but manufacturing precision deteriorates due to limited solder room for fluctuations
Solution Approach 1:
The patent changes the height parameter of the conductive pillars to a controlled range (30-50 um) with tight tolerance (within 5 um variation). This parameter control creates predictable gap distances between the die pads and conductive pillars, enabling finer pitch scaling while maintaining manufacturing precision and allowing sufficient solder room even at reduced pitches
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
An integrated circuit (IC) package comprises a substrate comprising electrical pathways; a plurality of landing pads at a top surface of the substrate; a plurality of conductive pillars electrically connected to respective landing pads, each of the conductive pillars having a height less than 30 micrometers, wherein the heights of the plurality of conductive pillars are within five micrometers of each other; an insulating material between adjacent ones of the plurality of conductive pillars, wherein a height of the insulating material is within 5 micrometers of the height of one of the conductive pillars; and a die electrically coupled to the plurality of conductive pillars.