Planar Resistive Memory Integration via Single Damascene Stacking
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Solution Overview
Problem
Existing methods for integrating two-terminal resistive memory cells on silicon wafers do not scale well below 20 nm and are costly, particularly in planar arrangements.
Innovation Solution
A single damascene structure is formed with reduced lithography steps, using a dielectric layer to vertically stack two-terminal resistive memory cells, which includes Conductive Metal Oxide (CMO) layers and Insulating Metal Oxide (IMO) layers, allowing for efficient fabrication with fewer photomasks and steps, thereby reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods for integrating two-terminal resistive memory cells are used, then planar arrangement is achieved, but manufacturing cost increases and scalability below 20 nm is lost
Solution Approach 1:
The patent transitions from planar to three-dimensional integration by vertically stacking multiple memory layers above the substrate. This dimensional change enables continued scaling below 20 nm by utilizing the vertical dimension, thereby avoiding the manufacturing cost and complexity penalties associated with further planar lithography scaling.
2Ease of manufacture
If reduced lithography steps are used, then manufacturing cost decreases, but fabrication process complexity must be managed
Solution Approach 1:
The patent merges multiple fabrication operations into a single damascene structure formation process. By combining the formation of conductive plugs, vias, and interconnect structures into one integrated process step, the number of lithography steps is reduced, lowering manufacturing cost while the process complexity is managed through consolidation rather than simplification.
3Ease of manufacture
If fewer photomasks and fabrication steps are used, then manufacturing cost decreases, but die yield must be maintained
Solution Approach 1:
The patent performs preliminary actions by forming the complete damascene structure and establishing all interconnect pathways before final memory cell formation. This preliminary structuring ensures that subsequent fabrication steps have pre-defined pathways and alignment references, reducing the risk of defects and maintaining high die yield even with fewer overall fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower manufacturing costs and higher die yields due to fewer fabrication steps, enabling effective integration of resistive memory cells in a planar configuration that can be scaled below 20 nm.
Implementation Method 1
a voltage drop across the electrolytic tunnel barrier can cause an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide and into the electrolytic tunnel barrier
Implementation Method 2
a voltage drop across the electrolytic tunnel barrier can cause an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions
Implementation Method 3
When certain mixed valence conductive oxides (e.g., praseodymium-calcium-manganese-oxygen—PCMO perovskites and lanthanum-nickel-oxygen—LNO perovskites) change valence, their conductivity changes
Implementation Method 4
oxygen accumulation in certain electrolytic tunnel barriers (e.g., yttrium stabilized zirconia—YSZ) can also change conductivity
Data Source
AI summary
In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.