Planar Schottky Contact Etch for Trench FET Leakage Reduction
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Solution Overview
Problem
In semiconductor power devices with integrated trench FET and Schottky diode structures, conventional Schottky contact etch techniques result in poor barrier metal step coverage and high leakage current due to inadequate topography and additional process steps.
Innovation Solution
A Schottky contact etch process with reduced dielectric to silicon selectivity is employed, eliminating the need for intermediate soft etch steps and achieving a more planar surface by etching dielectric and semiconductor materials at similar rates, allowing for a substantially planar barrier metal formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a selective dielectric etch is carried out to form the Schottky contact opening, then the Schottky contact opening is formed as defined by remaining dielectric portions, but the resulting topography is not suitable for forming the barrier metal
Solution Approach 1:
The patent changes the etch selectivity parameter between dielectric and silicon materials. By using an etch process with reduced selectivity (etching dielectric and silicon at similar rates rather than selectively etching only dielectric), the resulting topography becomes substantially planar, which is suitable for barrier metal formation while still defining the Schottky contact opening.
2Shape
If a selective soft etch of the silicon is carried out to improve the topology, then the topography is somewhat improved, but the barrier metal still has poor step coverage and additional process steps are added
Solution Approach 1:
The patent extracts and eliminates the intermediate soft etch step from the process sequence. By using an etch process with reduced dielectric-to-silicon selectivity from the beginning, the topology is improved directly during the Schottky contact opening formation, removing the need for the separate soft etch step and reducing overall process complexity.
3Shape
If a selective soft etch of the silicon is carried out to improve the topology, then the topography is somewhat improved, but the source contact metal fill characteristics are adversely affected
Solution Approach 1:
The patent changes the etch selectivity parameter to reduce the difference between dielectric and silicon etch rates. This results in a substantially planar surface that provides good step coverage for barrier metal and does not adversely affect source contact metal fill characteristics, unlike the selective soft etch approach.
4Manufacturing precision
If conventional Schottky contact etch techniques are used, then the Schottky contact opening is formed, but the leakage current is high
Solution Approach 1:
The patent changes the etch selectivity parameter between dielectric and silicon materials. By using an etch process with reduced selectivity that etches both materials at similar rates, a substantially planar surface is achieved, which enables proper barrier metal formation and results in significantly reduced drain-source leakage current (by a factor of 10 compared to conventional techniques).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces drain-source leakage current by a factor of 10 and eliminates the need for additional process steps, resulting in improved topography and reduced leakage.
Implementation Method 1
A Schottky contact etch process with reduced dielectric to silicon selectivity is employed, eliminating the need for intermediate soft etch steps and achieving a more planar surface by etching dielectric and semiconductor materials at similar rates
Data Source
AI summary
A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the top surface of the semiconductor layer adjacent the trench so as to form a Schottky contact with the top surface of the semiconductor layer adjacent the trench. A surface of the semiconductor layer in the Schottky region is lower relative to a surface of the semiconductor layer in the FET region.