Planar Schottky FET Layout for Low-Leakage Dense Circuits
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Solution Overview
Problem
The production of complex circuits with small field effect transistors is time-consuming, error-prone, and results in significant energy loss and heat dissipation due to leakage currents, making it challenging to achieve efficient and cost-effective manufacturing while maintaining optimal transistor properties.
Innovation Solution
A field effect transistor arrangement with a planar channel layer made of undoped semiconductor material, utilizing an adjustment electrode on the substrate's underside and barrier control electrodes to modulate charge carrier concentration and current flow, featuring midgap Schottky barriers and a control electrode design that allows for efficient control of current flow with minimal power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of field effect transistors are continuously reduced to increase transistor density, then the number of transistors per area increases, but manufacturing complexity and error rates increase significantly
Solution Approach 1:
The transistor structure is segmented into distinct functional regions: undoped channel layer, midgap Schottky barrier contact areas, control electrode regions, and barrier control electrode regions. This segmentation allows each region to be optimized independently for its specific function while simplifying the overall manufacturing process by using standardized fabrication steps for each segment.
Solution Approach 2:
Different regions of the transistor structure are assigned different material properties and doping states: the channel layer is undoped for high mobility, the contact areas have midgap Schottky barriers for carrier selectivity, and the control electrode regions have specific doping for field control. This local differentiation of properties enables precise control of electrical characteristics without increasing manufacturing complexity.
2Area of moving object
If field effect transistors are made smaller to increase circuit density, then area is reduced, but leakage currents increase causing energy loss and heat dissipation
Solution Approach 1:
Midgap Schottky barrier contact areas are introduced as intermediary structures between the metal electrodes and the semiconductor channel. These Schottky barriers act as selective filters that block leakage currents while allowing controlled carrier injection, thereby reducing energy loss from unwanted current flow in miniaturized transistors.
Solution Approach 2:
The transistor design utilizes changes in electrical parameters through voltage control: the control electrode applies electric fields to modulate the channel conductivity, and the barrier control electrodes adjust the Schottky barrier heights. This dynamic parameter control allows the transistor to operate with minimal leakage currents even at reduced dimensions.
3Quantity of substance
If conventional FET structures are used with doped channel layers, then majority charge carrier concentration is sufficient, but switching times are slower and power losses are higher
Solution Approach 1:
Instead of using doped semiconductor material to increase charge carrier concentration, the invention inverts the approach by using an undoped channel layer and generating carriers dynamically through electric field control. This inversion enables faster switching times because carriers are induced only when needed, rather than being present continuously as in doped structures.
Solution Approach 2:
The channel layer transitions from a static doped structure to a dynamic undoped structure where charge carrier concentration is controlled in real-time by the control electrode. This dynamic control allows the channel to switch between conductive and insulating states rapidly, reducing switching times and minimizing power losses during transitions.
4Adaptability or versatility
If CMOS technology is used with both p-channel and n-channel transistors, then circuit functionality is achieved, but the number of transistors required doubles compared to single-type logic
Solution Approach 1:
The field effect transistor structure is designed as a universal platform that can function as either p-channel or n-channel transistor depending on the applied voltage polarity and material selection. The same basic structure with undoped channel, Schottky barriers, and control electrodes can be configured for different transistor types, eliminating the need for separate optimized structures for each type and reducing overall transistor count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables cost-effective production of field effect transistors with improved switching times and reduced power losses, allowing for the creation of complex circuits with high density and low power consumption, while maintaining control over transistor properties.
Implementation Method 1
a contact area between the source electrode and the planar channel layer and a contact area between the drain electrode and the planar channel layer are each configured as a midgap Schottky barrier
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The invention relates to a field effect transistor arrangement having a planar channel layer (1) consisting of semiconductor material, the whole surface of the underside of said layer being applied to an upper side of an electrically insulating substrate layer (2) and the upper side of said planar channel layer being covered by an insulation layer (3). The arrangement has a source electrode (6) on a first side edge of the channel layer (1) and a drain electrode (7) on a second side edge of the channel layer (1) and a control electrode (9) arranged above the channel layer (1). An adjusting electrode (5) is arranged on an underside of the substrate layer (2). A contact region (8) between the source and drain electrodes (6) and the planar channel layer (1) is in each case configured as a midgap Schottky barrier. A respective barrier control electrode (10) is arranged in the vicinity of the contact region (8) of the source electrode (6) and of the drain electrode (6). Each barrier control electrode (10) can have a section (11) that projects outwards in the direction of the planar channel layer (1).