Planar Semiconductor Device Reducing Parasitic Capacitance
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from signal delay due to parasitic capacitance, leading to degraded image quality, especially with increasing screen size and resolution, and occupy more area compared to planar transistors, which have stable semiconductor characteristics and high reliability but are complex to manufacture.
Innovation Solution
A planar-type semiconductor device with an oxide semiconductor film, featuring a structure with a first conductive film, insulating films, an oxide semiconductor film with different impurity element concentrations, and a capacitor design that includes a lower electrode, inter-electrode insulating films, and upper electrodes, utilizing silicon nitride films and oxygen-rich oxide insulating films to reduce parasitic capacitance and enhance manufacturing simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor is used, then the manufacturing process is simple and manufacturing cost is low, but signal delay increases due to parasitic capacitance and image quality degrades
Solution Approach 1:
The patent inverts the conventional transistor structure by placing the gate electrode at the bottom instead of at the top, creating an inverted staggered transistor configuration. This inversion resolves the contradiction by maintaining manufacturing simplicity while reducing parasitic capacitance between the gate and source/drain electrodes, thereby decreasing signal delay and improving image quality in display devices
2Ease of manufacture
If an inverted staggered transistor is used, then manufacturing cost is low, but the occupation area is larger than planar transistors
Solution Approach 1:
The patent utilizes vertical layering in the inverted staggered transistor structure, stacking functional layers (gate electrode, insulating films, source/drain electrodes) in the vertical dimension. This dimensional approach allows compact integration while maintaining the manufacturing advantages of the inverted structure, effectively reducing the horizontal occupation area compared to conventional planar transistors
3Reliability
If a planar transistor is used, then semiconductor characteristics are stable and reliability is high, but the manufacturing process is complex
Solution Approach 1:
The patent applies structural inversion to simplify manufacturing while preserving reliability. By inverting the transistor configuration to place the gate at the bottom, the patent achieves both manufacturing simplicity and stable semiconductor characteristics, eliminating the need for complex planar manufacturing processes while maintaining high reliability
Data Source
AI summary
A semiconductor device includes a transistor and a capacitor. The transistor includes a first conductive film; a first insulating film including a film containing hydrogen; a second insulating film including an oxide insulating film; an oxide semiconductor film including a first region and a pair of second regions; a pair of electrodes; a gate insulating film; and a second conductive film. The capacitor includes a lower electrode, an inter-electrode insulating film, and an upper electrode. The lower electrode contains the same material as the first conductive film. The inter-electrode insulating film includes a third insulating film containing the same material as the first insulating film and a fourth insulating film containing the same material as the gate insulating film. The upper electrode contains the same material as the second conductive film. A fifth insulating film containing hydrogen is provided over the transistor.