Planar Semiconductor Surface via Voltage-Selective PEC Etching
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Solution Overview
Problem
Wide-gap semiconductors face challenges in growing defect-free single crystals on low-cost substrates like silicon and silicon oxide due to lattice mismatches, leading to poor crystal quality and nonuniform film surfaces, limiting their use in integrated photonic and electro-optical devices.
Innovation Solution
A method involving a workpiece with multiple etch stop layers and photo-electrochemical etching is used to selectively remove these layers, achieving a planar semiconductor surface by biasing the workpiece to different voltages, ensuring faster removal of each layer, thereby reducing thickness variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wide-gap semiconductors are grown on low-cost substrates like silicon and silicon oxide, then cost is reduced, but crystal quality deteriorates due to lattice mismatches causing defects
Solution Approach 1:
The invention segments the semiconductor structure into multiple functional layers: a low-cost substrate, buffer layers, and active device layers. This segmentation allows the substrate to be inexpensive while the active layers maintain high crystal quality, resolving the contradiction between substrate cost and crystal quality.
Solution Approach 2:
The invention introduces buffer layers as intermediary structures between the low-cost substrate and the active semiconductor layers. These buffer layers act as mediators that accommodate lattice mismatches and prevent defect propagation, enabling high-quality crystal growth on inexpensive substrates.
2Device complexity
If conventional etching methods are used on wide-gap semiconductors, then process simplicity is maintained, but surface uniformity deteriorates with nonuniform film surfaces across the wafer
Solution Approach 1:
The invention changes the etching parameters by applying photo-electrochemical etching with controlled voltage bias and UV illumination. This parameter change enables selective etching of sacrificial layers while preserving the active semiconductor layers, achieving uniform surface profiles across the wafer that are suitable for nanoscale device fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smooth, planar semiconductor surface with less than 10 nm total thickness variation over a 100 mm diameter wafer, enabling precise fabrication of nanoscale structures for advanced MEMS and photonic quantum devices.
Implementation Method 1
etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer
Implementation Method 2
etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer
Data Source
AI summary
A method for producing a planar semiconductor surface includes forming a workpiece that has a carrier substrate, one or more insulating layers, a semiconductor layer, a first etch stop layer, and a second etch stop layer; forming a contact on the workpiece; biasing the workpiece to a second voltage through the contact; etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer; biasing the workpiece to a first voltage through the contact; and etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer to produce a semiconductor device with a planar surface on the semiconductor layer.