Planar Silicon Optical Structure With Narrow Slot
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing silicon-based electro-optic modulators face challenges with high VπLπ values and optical losses due to non-planar structures and imperfections in fabrication techniques, making them difficult to integrate with other optical devices and limiting their performance in terms of speed and integration density.
Innovation Solution
A method of fabricating an optical structure using anisotropic wet etching to create a non-parallel side wall in a silicon substrate, followed by deposition of an insulating material and recrystallization of additional silicon layers to form a single crystal structure with a narrow slot, allowing for a planar configuration that reduces optical losses and enhances integration with other devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a stacked non-planar structure is used to achieve high-speed modulation via carrier accumulation, then modulation speed is improved, but device complexity and difficulty of integration with other optical devices increase
Solution Approach 1:
The patent transitions from a three-dimensional stacked non-planar structure to a two-dimensional planar structure by forming the insulating layer within the silicon layer itself using lateral epitaxial overgrowth. This dimensional reduction maintains the capacitor-type structure necessary for carrier accumulation while enabling planar integration with other optical devices such as ring resonators and photonic crystal waveguides.
2Ease of manufacture
If conventional slot fabrication techniques are used to create a planar configuration, then ease of integration is improved, but optical losses increase due to surface roughness and interface imperfections
Solution Approach 1:
The patent replaces mechanical fabrication techniques (making slots and filling them with dielectric material) with a chemical epitaxial growth process. The lateral epitaxial overgrowth technique allows the insulating layer to conformally coat the silicon surface and self-smooth, eliminating surface roughness and interface imperfections that cause optical losses while maintaining planar configuration for easy integration.
3Strength
If long interaction lengths are used to compensate for weak electro-optic effect, then modulation depth is improved, but device length increases leading to higher propagation loss
Solution Approach 1:
The patent concentrates the electro-optic interaction in a localized region by forming a narrow slot (50-200 nm width) with the insulating layer, creating a high electric field density in a confined space. This local concentration of the electro-optic effect allows achieving sufficient modulation depth with shorter device lengths, reducing propagation losses while maintaining effective modulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a compact, low-loss optical structure with improved integration capabilities and high-speed electro-optic modulation efficiency, enabling shorter device lengths and reduced optical propagation loss.
Implementation Method 1
using etching to remove part of the silicon layer and define a side wall which is non-parallel to the insulating surface of the substrate
Implementation Method 2
forming a layer of insulating material over the side wall
Implementation Method 3
crystallising the silicon of the further layer so that it forms a single crystal structure with the silicon in the layer, in which the crystallisation uses the silicon layer as a seed
Data Source
Figure 1~3
Figure 4~6
Figure 7~10(k)
AI summary
A method of fabricating an optical structure comprises providing a layer of single crystal crystalline silicon supported on an insulating surface of a silicon substrate; using etching to remove part of the silicon layer and define a side wall which is non-parallel to the insulating surface of the substrate;forming a layer of insulating material over the side wall; forming a further layer of silicon over at least the insulating material; and removing the silicon of the further layer to a level of the layer of silicon such that the layer of insulating material occupies a slot between a portion of silicon in the layer and a portion of silicon in the further layer, a thickness of the layer of insulating material defining a width of the slot.