Semiconductor Trench Structure for Planar Silicon Pillar Contacts
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving precise control of element configuration due to issues like undesired oxidation of silicon pillars, leading to rounded edges and uneven surfaces, which result in reduced contact area and high electrical resistance.
Innovation Solution
A method is developed to create a planar surface for silicon pillars by forming dielectric and oxide layers, followed by precise etching and planarization processes to maintain a flat surface, thereby avoiding electrical disconnection and high resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon pillars are formed without protective layers, then the fabrication process is simpler, but the silicon pillars undergo undesired oxidation leading to rounded edges and uneven surfaces
Solution Approach 1:
A dielectric layer is introduced as an intermediary protective layer between the silicon pillar and the oxidation environment. This dielectric layer prevents direct oxidation of the silicon pillar while maintaining process feasibility, thereby resolving the contradiction between fabrication simplicity and surface precision.
Solution Approach 2:
The dielectric layer creates an inert protective environment around the silicon pillar, preventing oxidation by isolating the silicon from oxygen exposure during subsequent fabrication steps. This approach maintains surface flatness and edge sharpness without complicating the overall fabrication process.
2Stability of the object's composition
If silicon pillars are oxidized, then the surface becomes more stable chemically, but the contact area is reduced and electrical resistance increases
Solution Approach 1:
The dielectric layer serves as a mediator that provides chemical stability and oxidation protection to the silicon pillar while preventing the formation of oxidized surfaces that would increase electrical resistance. This intermediary layer maintains both chemical stability and electrical connectivity.
Solution Approach 2:
By creating an inert protective environment through the dielectric layer, the silicon pillar maintains its original surface properties and electrical characteristics while being protected from oxidation. This resolves the contradiction between achieving chemical stability through oxidation and maintaining electrical connectivity.
3Productivity
If conventional deposition methods are used, then the process is faster and simpler, but precise control of element configuration is difficult to achieve
Solution Approach 1:
The deposition process is segmented into multiple sequential steps (first dielectric layer, then second dielectric layer) with intermediate planarization steps. This segmentation allows for precise control of each layer's thickness and configuration while maintaining overall process efficiency, resolving the contradiction between fabrication speed and configuration precision.
Solution Approach 2:
Planarization steps are performed preliminarily between dielectric layer depositions to ensure that subsequent layers are deposited on flat surfaces. This preliminary action enables precise control of element configuration in subsequent steps without significantly extending the overall fabrication time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance and product yield by ensuring a stable and planar surface for silicon pillars, enhancing electrical connectivity and reducing resistance.
Implementation Method 1
depositing a conductive material to partially fill the first trench
Implementation Method 2
depositing a conductive material to partially fill the first trench
Implementation Method 3
depositing an isolation material in the first trench to cap a portion of the conductive material exposed around the insulative piece
Implementation Method 4
depositing an isolation material in the first trench to cap a portion of the conductive material exposed around the insulative piece
Data Source
AI summary
The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A planar surface of a silicon pillar is provided. At least one first trench is created in a substrate. A conductive material is deposited to partially fill the first trench. An insulative piece is formed in the first trench and extends into the conductive material. An isolation material is deposited in the first trench to cap the conductive material exposed around the insulative piece. The depositing of the isolation material further includes enclosing at least one void in the isolation material.


