Planar-Staggered RRAM Array for DNN Accelerator Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current deep neural network (DNN) accelerators face challenges in power efficiency and area consumption due to high power and area requirements for convolution operations in RRAM arrays, particularly with Manhattan layouts that necessitate matrix unfolding and input regeneration, leading to increased clock cycles and interface accesses, and are susceptible to parasitic I-R drop and nonlinearity.
Innovation Solution
A planar-staircase array layout with staggered bit-lines and word-lines is introduced, which reduces input regeneration and power consumption by auto-shifting inputs and enabling parallel output generation, combined with a hardware-aware in-memory compute method that maps arbitrary floating-point matrix values to finite RRAM conductances, reducing device variability and nonlinearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If planar crossbar arrays with Manhattan layout are used for convolution execution, then the basic computation function is achieved, but input regeneration and massive input matrix unfolding are required leading to increased power and area consumption
Solution Approach 1:
The patent transitions from a 2D Manhattan layout to a 3D stacked crossbar array architecture. By stacking multiple RRAM layers vertically and implementing staggered bit-line connections between layers, the system eliminates the need for input regeneration and matrix unfolding operations, thereby reducing power consumption while maintaining computational functionality.
Solution Approach 2:
The patent creates staggered copies of bit-lines across different RRAM layers, where bit-lines in upper layers are horizontally displaced relative to lower layers. This copying strategy enables direct access to input values across layers without regeneration, reducing the computational overhead and power consumption associated with input matrix unfolding.
2Productivity
If 3D-arrays with staircase routing are used to improve throughput, then throughput is enhanced, but via-resistance increases limiting the number of RRAM layers and increasing peripheral circuitry
Solution Approach 1:
The patent segments the 3D crossbar array into multiple RRAM layers with staggered bit-line connections. Instead of using continuous staircase routing that increases via-resistance, the system divides the computation across discrete layers where each layer has its own bit-lines that are horizontally offset from adjacent layers, reducing the cumulative via-resistance effect.
Solution Approach 2:
The patent applies local quality by implementing staggered bit-line connections only where necessary between specific RRAM layers, rather than using uniform staircase routing throughout. This localized approach maintains throughput enhancement while minimizing the increase in peripheral circuitry and via-resistance.
3Adaptability or versatility
If differential technique is used for signed floating-point computations, then computation capability is improved, but clock cycles and interface accesses increase impeding throughput improvement and power reduction
Solution Approach 1:
The patent extracts the sign information from floating-point numbers and handles it separately through the staggered bit-line architecture. By representing numbers in a format where sign and magnitude are handled differently and utilizing the spatial arrangement of staggered bit-lines, the system can perform signed floating-point computations without requiring the overhead of differential techniques, thus reducing clock cycles and interface accesses.
Data Source
AI summary
A memory device for deep neural network, DNN, accelerators, a method of fabricating a memory device for deep neural network, DNN, accelerators, a method of convoluting a kernel [A] with an input feature map [B] in a memory device for a deep neural network, DNN, accelerator, a memory device for a deep neural network, DNN, accelerator, and a deep neural network, DNN, accelerator. The method of fabricating a memory device for deep neural network, DNN, accelerators comprises the steps of forming a first electrode layer comprising a plurality of bit-lines; forming a second electrode layer comprising a plurality of word-lines; and forming an array of memory elements disposed at respective cross-points between the plurality of word-lines and the plurality of bit-lines; wherein at least a portion of the bit-lines are staggered such that a location of a first cross-point between the bit-line and a first word-line is displaced along a direction of the word-lines compared to the cross-point between said bit-line and a second word-line adjacent the first word-line; or wherein at least a portion of the word-lines are staggered such that a location of a cross-point between the word-line and a first bit-line is displaced along a direction of the bit-lines compared to a cross-point between said word-line and a second bit-line adjacent the first bit-line.