Planar-Termination Trench Gate Wide-Bandgap JFETs for Breakdown Control

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Solution Overview

Problem

Conventional power JFETs face challenges in precise control of guard ring formation due to additive processing tolerances, leading to variability in doping concentrations and shapes, which increases susceptibility to premature avalanche breakdown and gate-drain leakage.

Innovation Solution

The JFETs feature a termination region with a planar upper surface, allowing separate optimization of guard ring formation and eliminating trench etching tolerances, thereby reducing variability and optimizing electric field distribution without p-n junctions in the sidewalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional trench etching processes are used in the termination region, then guard ring formation can be integrated into the same process, but additive processing tolerances accumulate leading to variability in doping concentrations and shapes

Engineering Contradiction:

Improveprocess integrationVSAvoidguard ring doping concentration and shape control

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the device into two distinct regions with different surface topographies: the active region with trench structures and the termination region with a planar upper surface. This segmentation allows separate optimization of processing for each region, preventing tolerance accumulation while maintaining process integration benefits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The termination region is given a distinct planar surface quality different from the active region. This local quality difference enables precise control of guard ring formation in the termination region without being affected by the trench etching tolerances present in the active region.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If a planar upper surface is used in the termination region, then guard ring formation can be independently optimized, but the device structure becomes more complex compared to uniform trench structures

Engineering Contradiction:

Improveguard ring formation controlVSAvoidtermination region structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The device structure is segmented into active and termination regions with different surface characteristics. This segmentation adds structural complexity but enables independent optimization of guard ring formation in the termination region, achieving better manufacturing precision.

Inventive Principle:

Principle #1Segmentation

3Reliability

If trenches are etched in the termination region, then electric field distribution can be managed, but p-n junctions form in the sidewalls increasing susceptibility to avalanche breakdown and gate-drain leakage

Engineering Contradiction:

Improveresistance to avalanche breakdown and gate-drain leakageVSAvoidelectric field crowding effects

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the trench structure from the termination region, leaving only a planar upper surface. This removes the harmful p-n junctions that would form in trench sidewalls, eliminating the source of avalanche breakdown and gate-drain leakage while maintaining electric field management through alternative means.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250338571A1Trench gate wide bandgap junction field effect transistors with termination regions having planar upper surfaces

Publication Date: 2025.10.30 WOLFSPEED INC

AI summary

JFETs are provided that comprise a wide bandgap semiconductor layer structure comprising an active region and a termination region. The termination region comprises a plurality of termination structures. A first major surface of the semiconductor layer structure in the active region comprises a plurality of spaced-apart mesas and the first major surface of the semiconductor layer structure in the termination region is a planar surface.