Planar Thin Film Transistor Structure for Reduced Parasitic Capacitance
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Solution Overview
Problem
Conventional oxide thin film transistors (TFTs) have complex structures and processes, leading to performance reduction due to contamination and high resistance regions, requiring a simplified structure and process to maintain high performance.
Innovation Solution
A thin film transistor with a simplified structure where the source, drain, and gate are formed in the same layer, using a 5-Mask process, and ion implantation to create conductive contact layers that reduce contact resistance and parasitic capacitance, along with an isolation layer to prevent light interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional top gate type oxide TFT structure is used, then high performance can be achieved, but the device structure becomes complex and the manufacturing process becomes complicated requiring 6-mask processes
Solution Approach 1:
The patent merges the gate, source, and drain into the same layer, forming a planar structure where the gate electrode and source/drain electrodes are coplanar. This consolidation simplifies the device structure while maintaining the essential transistor functionality, directly addressing the complexity issue of conventional multi-layer top gate structures.
Solution Approach 2:
The patent transitions from a vertical multi-layer architecture to a horizontal planar architecture by arranging gate, source, and drain electrodes in the same layer. This dimensional reorganization reduces structural complexity while preserving device performance through optimized electrode spacing and configuration.
2Device complexity
If multiple pattern processes are used to fabricate the TFT, then the structure can be formed, but the function film layers become contaminated and performance is reduced
Solution Approach 1:
The patent combines multiple electrode formations (gate, source, drain) into a single pattern process step. By forming all three electrodes in the same layer simultaneously through one mask and etch process, the number of pattern processes is reduced from six to one, minimizing contamination exposure and protecting film integrity.
Solution Approach 2:
The patent performs preliminary planning of the electrode configuration to enable all electrodes to be formed in a single process step. The coplanar geometry and material selection are designed in advance to allow unified fabrication, preventing the need for sequential processing that would increase contamination risk.
3Reliability
If conventional multi-layer structure is used, then high performance can be achieved, but non-channel high resistance regions and parasitic capacitance increase
Solution Approach 1:
The patent merges the gate, source, and drain into a single layer configuration, eliminating the vertical stacking that creates interface resistance and parasitic capacitance between layers. This planar integration reduces the number of interfaces and contact points, directly lowering parasitic effects while maintaining electrical performance.
Solution Approach 2:
The patent extracts the vertical layering concept and replaces it with a planar arrangement. By removing the multi-layer stacking approach, the patent eliminates the associated interface resistance and parasitic capacitance that arise from vertical interfaces, achieving lower parasitic effects through dimensional simplification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The simplified structure and process improve electrical properties by reducing non-channel high resistance regions and parasitic capacitance, enhancing the performance and reliability of the TFTs.
Implementation Method 1
using a 5-Mask process, and ion implantation to create conductive contact layers that reduce contact resistance and parasitic capacitance
Data Source
AI summary
A thin film transistor (TFT) and manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor comprises a substrate; an active layer formed on the substrate; a first conductive contact layer and a second conductive contact layer formed on the active layer; an etch-stop layer formed over the first contact layer and the second contact layer; and a source connected with the first contact layer, a drain connected with the second contact layer and a gate arranged between the source and the drain formed over the etch-stop layer. The TFT has a simple structure and better performance.