Planar and Tri-Gate Transistor Integration on Substrate

The patent applies local quality by creating different transistor strengths not through varying diffusion widths, but through localized changes in gate electrode length. Each transistor type (pass-gate, pull-down, pull-up) receives a specific gate length tailored to its function, while all transistors share the same uniform diffusion width W. This allows independent optimization of each transistor's strength characteristics without affecting the uniformity of the diffusion structure across the substrate.

The patent segments the transistor strength control parameter into gate length H rather than using diffusion width W. By separating the control mechanism, the diffusion region can maintain uniform width for simplified patterning, while the gate electrode length is independently adjusted for each transistor type to achieve the required strength variations. This segmentation resolves the contradiction between uniformity and differentiation.

The invention applies local quality by maintaining uniform diffusion width W across all transistors for simplified lithography patterning, while achieving different transistor strengths through localized variations in gate electrode length H. This approach eliminates the need for complex mask designs required for variable width diffusions, as the uniform diffusion can be patterned with standard lithography techniques.

Instead of varying diffusion width to control transistor strength (conventional approach), the patent inverts the control mechanism by varying gate length while keeping diffusion width constant. This inversion simplifies the lithography process for the diffusion region, as uniform width features are easier to pattern with high precision than variable width features requiring jog structures.

The patent achieves local quality in transistor strength control through gate length variation rather than diffusion width variation. This eliminates the need for jog structures in the diffusion regions, allowing for more compact and efficient layout of the SRAM cell. The uniform diffusion width enables tighter packing of transistor components, reducing the overall cell area.

The patent moves the strength control parameter from the lateral dimension (diffusion width) to the longitudinal dimension (gate length). By controlling transistor strength through gate length H rather than diffusion width W, the design achieves the required differentiation without the area-penalty jog structures that would be needed to create variable width diffusions in the lateral direction.