Planar Variable Resistance Memory Cell Architecture

The patent segments the memory cell structure into distinct functional layers (variable resistance layer, channel layer, gate layer) that can be independently optimized. This segmentation allows the access device to control multiple memory cells through shared channel and gate structures, improving the access device-to-memory cell ratio and enabling higher memory density while maintaining reliable data storage through the variable resistance layer's distinct functional regions.

The patent implements multi-functionality by designing the channel layer and gate layer to serve multiple memory cells simultaneously. The channel layer acts as a shared conduction path for multiple variable resistance layers, and the gate layer provides unified control for multiple memory cells, enabling one access device to control multiple memory cells. This reduces read latency by allowing parallel access to multiple cells while maintaining data storage reliability through the variable resistance mechanism.

The patent merges multiple memory cell structures by combining shared channel layers and gate layers that control multiple variable resistance layers. This merging reduces the total number of access devices required, improving the access device-to-memory cell ratio and enabling higher memory density. The shared structures allow coordinated control of multiple cells, reducing the cumulative current requirements compared to independent control of each cell, thus lowering overall programming current requirements while maintaining high density.