Planarization Resistance Patterns for MML Semiconductor Stability
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Solution Overview
Problem
The manufacturing of merged memory with logic (MML) semiconductor devices is challenging due to the height difference between memory and logic regions, leading to unstable planarization and via plug formation, as the processes for these regions are not interchangeable.
Innovation Solution
The MML semiconductor device incorporates planarization resistance patterns formed on the same material as the capacitor dielectric and top electrode, with a capping layer extending over the second interlayer dielectric layer, and third via plugs connected to the top electrode of capacitors, allowing for simultaneous formation of capacitors in the memory region and planarization resistance patterns in the logic region, stabilizing the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If capacitors are formed in the memory region to a height of several thousand Å while logic region capacitors are formed to a height of several hundred Å or not formed, then the memory function and logic function can be integrated, but the planarization process and via plug formation become unstable due to height difference
Solution Approach 1:
The patent applies local quality by forming planarization resistance patterns selectively in the logic region while forming capacitors in the memory region. These resistance patterns are made from the same material as the capacitor dielectric and top electrode, creating localized structures that provide planarization resistance only where needed (in the logic region) without interfering with capacitor formation in the memory region. This allows each region to have optimized local properties.
Solution Approach 2:
The planarization resistance patterns are formed in advance during the capacitor formation process. The resistance patterns are created simultaneously with the capacitor dielectric and top electrode layers, before the planarization process occurs. This preliminary formation ensures that the resistance patterns are already in place to prevent excessive etching and polishing during subsequent planarization steps.
2Reliability
If manufacturing processes are made interchangeable for both memory and logic regions, then process stability improves, but the different structural requirements of capacitors (large in memory, small or absent in logic) cannot be met
Solution Approach 1:
The patent achieves universality by using the same material for both the capacitor dielectric/top electrode and the planarization resistance patterns. The resistance patterns serve multiple functions: they provide planarization resistance during CMP processes, and they can also serve as conductive structures in the logic region. This multi-functional approach allows a single material system to satisfy different structural requirements in different regions.
Solution Approach 2:
The planarization resistance patterns act as an intermediary element that mediates between the conflicting requirements of memory and logic regions. These patterns are formed in the logic region to provide the necessary planarization resistance, while allowing the memory region to have its capacitor structures. The resistance patterns effectively bridge the gap between the two different structural requirements, enabling process stability across the entire device.
3Reliability
If planarization resistance patterns are formed in the logic region, then excessive etching and polishing are prevented, but additional manufacturing steps are required
Solution Approach 1:
The patent merges the formation of planarization resistance patterns with the capacitor formation process. Both the capacitor dielectric and the planarization resistance patterns are formed using the same deposition steps and materials. The resistance patterns are created as part of the same process sequence that forms the capacitor structures, rather than as a separate subsequent step. This combining of operations reduces the total number of manufacturing steps while still providing the necessary planarization resistance.
Data Source
AI summary
An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs.