Planarized Die Interconnect Substrate for Uniform Bump Heights

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Solution Overview

Problem

Variations in solder structures, such as bump top variations, lead to unreliable or faulty electrical signals in semiconductor devices due to inconsistencies in the height of interface structures, affecting the reliability of connections between semiconductor dies and substrates.

Innovation Solution

A die interconnect substrate with a bridge die and substrate interconnects, where the first and second interface structures are planarized to have the same surface height, reducing bump top variations and enhancing connection reliability by embedding a bridge die in an electrically insulating substrate with vertically extending substrate interconnects and forming interface structures connected to bridge die pads and substrate interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder structures are used to connect semiconductor dies to substrates, then electrical connections are established, but variations in bump top heights lead to unreliable electrical signals

Engineering Contradiction:
Improveconnection reliabilityVSAvoidbump top height consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a planarization layer before the final solder bump formation. This planarization layer pre-compensates for height variations, ensuring that when solder bumps are formed on top, their tops align at a consistent height. This preliminary structural preparation eliminates the need for post-forming adjustments and ensures reliable electrical connections without manufacturing precision issues.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the physical parameters of the interface structure by introducing a planarization layer with specific height compensation properties. By adjusting the thickness and material properties of this layer, the overall height variation of bump tops is controlled within acceptable ranges, transforming an uncontrolled parameter (bump height variation) into a controlled one through deliberate parameter selection.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If interface structures with varying heights are used, then connection flexibility is maintained, but electrical signal reliability deteriorates

Engineering Contradiction:
Improveconnection flexibilityVSAvoidelectrical signal reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The planarization layer is formed in advance to create a uniform surface for subsequent bump formation. This preliminary action allows the interface structure to maintain adaptability in accommodating different bump sizes and positions while ensuring that all bump tops reach the same height, thus preserving both connection flexibility and electrical signal reliability.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If additional planarization layers are added to reduce bump top variations, then connection reliability improves, but device complexity increases

Engineering Contradiction:
Improveconnection reliabilityVSAvoidinterface structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of planarizing the entire substrate surface, the patent applies the planarization layer locally only where bump structures will be formed. This localized approach reduces the overall complexity of the interface structure while still achieving the reliability benefit of uniform bump top heights. The solution focuses complexity only where it is functionally necessary.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11842981B2Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
Publication Date: 2023.12.12 INTEL CORP
  • US11842981B2 patent drawing
  • US11842981B2 patent drawing
  • US11842981B2 patent drawing

AI summary

Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.