Planarized Etch Stop Layer for MEMS Sensors
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Solution Overview
Problem
Existing etch stop layers in MEMS sensors are affected by topography of subjacent layers, leading to weak points and unintended etching, which compromises the sensitivity and reliability of capacitive MEMS sensors, particularly due to the need for thermal processes and potential over-etching.
Innovation Solution
A method involving the planarization of layers before depositing a thin etch stop layer with low surface roughness and low HF etch rate, using materials like silicon carbide or silicon nitride, to prevent topography-induced weak points and eliminate the need for high-temperature thermal processes, ensuring accurate and sensitive MEMS sensor manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional etch stop layer is deposited on structured bottom electrode, then the etch stop layer provides protection against over-etching, but the topography of subjacent layers creates weak points that compromise etching reliability
Solution Approach 1:
The patent applies planarization treatment to the structured bottom electrode before depositing the etch stop layer. This preliminary action removes surface irregularities and creates a flat substrate, preventing the formation of weak points in the subsequent etch stop layer while maintaining its protective function against over-etching
Solution Approach 2:
The patent introduces an intermediary planarization process between the bottom electrode formation and etch stop layer deposition. This intermediary step acts as a mediator that transforms the structured surface into a planar surface, ensuring both manufacturing precision and etching reliability
2Reliability
If a thick etch stop layer is used to prevent over-etching, then protection against subjacent material access is improved, but the electrical properties of capacitive sensor are degraded
Solution Approach 1:
The patent changes the surface parameter (roughness) of the substrate before depositing the etch stop layer. By planarizing the surface, the etch stop layer can be made thinner while maintaining uniform thickness and protective function, thereby preserving the electrical properties and sensitivity of the capacitive sensor
Solution Approach 2:
The patent applies planarization specifically to the regions where the etch stop layer will be deposited, creating locally optimized surface conditions. This allows the etch stop layer to achieve uniform thin thickness across the capacitor area, balancing protection and electrical performance
3Reliability
If thermal processes at elevated temperatures are used to form etch stop layer, then the etch stop layer provides adequate protection, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent replaces thermal processes with a planarization process (such as chemical-mechanical polishing or etch-back) to prepare the surface for etch stop layer deposition. This substitution eliminates the need for high-temperature thermal treatment while achieving the same protective function with reduced manufacturing complexity
Solution Approach 2:
The patent changes the process parameters from high-temperature thermal processing to low-temperature planarization followed by deposition. This parameter change maintains the protective quality of the etch stop layer while simplifying the manufacturing process and reducing equipment requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of thin, high-sensitivity etch stop layers that maintain electrical properties and prevent over-etching, enabling precise MEMS sensor manufacturing with reduced manufacturing costs and improved sensitivity, while integrating with CMOS technology for accurate and efficient sensor operation.
Implementation Method 1
depositing on top of the first planarized layer a second planarized layer of an ESL material with low HF etch rate
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 3A~3D
AI summary
The invention relates to a method for manufacturing a planarized etch-stop layer (13), ESL, for a hydrofluoric acid, HF, vapor phase etching process. The method comprises providing a first planarized layer (17) on top of a surface of a substrate (10), the first planarized layer (17) comprising a patterned and structured metallic material (20) and a filling material (22). The method further comprises depositing on top of the first planarized layer (17) the planarized ESL (13) of an ESL material (23) with low HF etch rate, wherein the planarized ESL (13) has a low surface roughness and a thickness of less than 150nm, in particular of less than 100nm.