Planarized Insulating Layer for Thin Film Transistor Gate Electrode
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Solution Overview
Problem
The existing methods for forming gate insulating layers in thin-film transistors result in exposed lateral surfaces of gate electrodes during etching, leading to disconnection issues and reduced electrical characteristics, particularly in high-resolution liquid crystal displays where the gate electrode thickness varies significantly.
Innovation Solution
A planarized insulating layer is formed at the lateral surface and upper portion of the gate electrode, followed by a gate insulating layer and active layer deposition, allowing for the formation of source and drain electrodes separated by a channel region, which reduces step height and enhances coverage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gate insulating layer is formed using conventional CVD process on a gate electrode with significant thickness variation, then the deposition process is simple and fast, but the lateral surface of the gate electrode is exposed and step height is large causing disconnection issues
Solution Approach 1:
A planarized insulating layer is formed on the substrate before forming the gate insulating layer. This preliminary action fills in the thickness variations of the gate electrode, creating a planar surface that enables subsequent gate insulating layer deposition without exposure or disconnection issues, while maintaining a relatively thin overall structure
Solution Approach 2:
The planarized insulating layer acts as an intermediary between the substrate and the gate insulating layer. It mediates the thickness variation problem of the gate electrode by providing a planar surface, allowing the gate insulating layer to be formed uniformly without directly contacting the uneven gate electrode surface
2Reliability
If the gate electrode thickness is increased to maintain electrical characteristics in high-resolution displays, then electrical performance is improved, but step height increases causing exposure and disconnection during etching
Solution Approach 1:
The planarized insulating layer is formed in advance to compensate for the thickness variation of the gate electrode. This allows the gate insulating layer to be deposited on a planar surface, preventing exposure during etching while maintaining the necessary gate electrode thickness for electrical performance
Solution Approach 2:
The planarized insulating layer is selectively formed only at regions where the gate electrode thickness varies significantly, providing local compensation where needed. This maintains the overall thin profile of the device while addressing specific areas of thickness variation that cause etching problems
3Manufacturing precision
If a thick gate insulating layer is formed to cover the lateral surface of the gate electrode, then coverage is improved, but the overall device thickness increases and subsequent element deposition becomes difficult
Solution Approach 1:
By forming the planarized insulating layer first, the gate insulating layer can be deposited on a planar surface with minimal thickness requirement. This preliminary planarization allows adequate coverage stability without needing a excessively thick gate insulating layer, thus controlling the overall device thickness
Solution Approach 2:
Instead of increasing the thickness of the gate insulating layer vertically to achieve coverage, the solution shifts to the horizontal dimension by forming the planarized insulating layer that extends over the lateral surface of the gate electrode. This dimensional shift provides coverage without excessive vertical thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents exposure of gate electrodes during etching, facilitates the deposition of subsequent elements, and improves the electrical characteristics of thin-film transistors, reducing failures and costs associated with high-resolution liquid crystal displays.
Implementation Method 1
a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode
Implementation Method 2
a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode
Data Source
AI summary
A thin-film transistor array substrate and a fabrication method thereof according to an embodiment of the present invention are disclosed to form an interlayer insulating layer, thereby reducing a failure occurred during the process subsequent to a gate electrode. The thin-film transistor disclosed according to the present invention may include a substrate, a gate electrode formed on the substrate, a planarized insulating layer formed at a lateral surface portion of the gate electrode and at an upper portion of the substrate, a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode, an active layer formed at an upper portion of the planarized insulating layer located at an upper side of the gate electrode, and a source electrode and a drain electrode formed on the active layer and separated from each other based on a channel region.