Planarized Lower Electrode for Variable Resistance Memory
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Solution Overview
Problem
Conventional variable resistance nonvolatile memory devices exhibit varying resistance change characteristics due to underlying layer shape and thickness variations, leading to bit errors and instability in large-capacity memory applications.
Innovation Solution
A semiconductor memory device configuration featuring a planarized lower electrode structure with a stacked variable resistance layer composed of transition metal oxides, where the second layer with higher oxygen content is locally short-circuited to stabilize resistance change, reducing variations in shape and thickness caused by the underlying layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional variable resistance element structure is used with underlying layers, then the device can be manufactured, but the resistance change characteristics vary due to shape and thickness variations of the underlying layer
Solution Approach 1:
The variable resistance layer is divided into a stacked structure consisting of a first variable resistance layer and a second variable resistance layer with different oxygen content percentages. This segmentation allows each layer to have optimized properties: the first layer provides the base resistance characteristics while the second layer with higher oxygen content stabilizes the resistance change through selective oxidation-reduction reactions at the interface, thereby reducing variation caused by underlying layer variations.
Solution Approach 2:
The patent applies local quality by creating a planarized lower electrode structure that is thicker above the contact plug than above the interlayer insulating layer. This local thickness variation compensates for the recess shape, ensuring that the variable resistance layer receives a uniform underlying surface. Additionally, the second variable resistance layer has locally higher oxygen content at the interface region to enable stable resistance change reactions.
2Ease of manufacture
If the variable resistance layer thickness varies due to underlying layer shape, then manufacturing is simplified, but resistance change characteristics become unstable
Solution Approach 1:
The lower electrode is planarized in advance before forming the variable resistance layer. By creating a planarized surface with controlled thickness distribution prior to depositing the variable resistance layer, the patent ensures that the variable resistance layer forms with uniform thickness regardless of the underlying contact plug recess shape. This preliminary planarization action prevents thickness variations from propagating to the variable resistance layer, ensuring stable resistance change characteristics.
3Reliability
If oxidation-reduction reactions occur at the interface, then resistance change is stabilized, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the chemical composition parameter by creating a stacked variable resistance layer structure where the second layer has a higher oxygen content percentage than the first layer. This parameter change enables selective oxidation-reduction reactions to occur preferentially at the interface between the second variable resistance layer and the electrode, stabilizing resistance change. The controlled oxygen content gradient provides a built-in mechanism that reduces sensitivity to interface quality variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces resistance change variations, enhancing the stability and reliability of large-capacity nonvolatile memory devices by ensuring consistent initial breakdown characteristics and minimizing bit errors.
Implementation Method 1
oxidation reaction and reduction reaction occur selectively at the interface between the upper electrode and the second variable resistance layer
Implementation Method 2
oxidation reaction and reduction reaction occur selectively at the interface between the upper electrode and the second variable resistance layer
Implementation Method 3
the top surface of the lower electrode can be made flat
Data Source
AI summary
Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode. The lower electrode, the variable resistance layer, and the upper electrode compose a variable resistance element.