Planarized Micro-Assembly via Capillary Polymer Embedding

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Solution Overview

Problem

Conventional methods for planarizing microelectronic chips on substrates are costly and complex, requiring substantial processing and introducing complications that reduce production yields, especially when interconnects need to span step edges.

Innovation Solution

Microelectronic chips are integrally embedded in a solid polymer substrate, where the polymer material melts and flows around the chips due to capillary forces, securing them without external alignment or etching, allowing for coplanar surfaces and straightforward interconnect formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional planarization methods (pre-patterning recesses, etching back, or opening vias) are used, then chip surfaces can be made coplanar with the substrate, but manufacturing costs increase substantially and production yields decrease due to complex processing steps

Engineering Contradiction:
Improvecoplanarity of chip surfaces with substrateVSAvoidprocessing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-forming protrusions on the substrate before chip placement. These protrusions are designed to automatically receive and hold the chips in a coplanar position when the chips are placed on the substrate, eliminating the need for post-placement planarization steps such as etching back or opening vias. This preliminary structuring of the substrate resolves the technical contradiction by achieving coplanarity through design rather than complex processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs self-service through the self-aligning and self-planarizing mechanism. When chips are placed on the substrate with pre-formed protrusions, the chips automatically settle into the protrusions and achieve coplanar alignment without requiring external alignment tools or additional processing steps. The structure itself provides the alignment and planarization function, eliminating the need for complex conventional planarization processes and thereby reducing manufacturing complexity while maintaining precision.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If conventional planarization methods are used, then chip surfaces can be made coplanar, but manufacturing costs increase due to substantial processing requirements

Engineering Contradiction:
Improvecoplanarity of chip surfaces with substrateVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-forming protrusions on the substrate before chip placement. These protrusions are designed to automatically receive and hold the chips in a coplanar position when the chips are placed on the substrate, eliminating the need for post-placement planarization steps such as etching back or opening vias. This preliminary structuring of the substrate resolves the technical contradiction by achieving coplanarity through design rather than complex processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs self-service through the self-aligning and self-planarizing mechanism. When chips are placed on the substrate with pre-formed protrusions, the chips automatically settle into the protrusions and achieve coplanar alignment without requiring external alignment tools or additional processing steps. The structure itself provides the alignment and planarization function, eliminating the need for complex conventional planarization processes and thereby reducing manufacturing complexity while maintaining precision.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces manufacturing costs and simplifies the process, maintaining chip spacing and preventing interconnect failures by avoiding step-like features, enabling reliable and cost-effective micro-assembly with conventional interconnect techniques.

Implementation Method 1

capillary (surface) forces cause the micro-objects to 'sink' only until the upper surface of each micro-object is planarized to (i.e., made co-planar with) the liquid surface

Methodology Applied
Scientific EffectCapillary forces: Capillary Action

Implementation Method 2

The uncured polymer layer is then heated to its melting point temperature such that the polymer material melts (liquefies)

Methodology Applied
Scientific EffectMelting: Melting

Implementation Method 3

subsequently cured using a higher curing temperature (and/or ultraviolet (UV) light) to form a cross-linked rigid film-like substrate

Methodology Applied
Scientific EffectCuring: Photopolymerisation

Data Source

PatentUS9396972B2Micro-assembly with planarized embedded microelectronic dies
Publication Date: 2016.07.19 GENESEE VALLEY INNOVATIONS LLC
  • US9396972B2 patent drawing
  • US9396972B2 patent drawing
  • US9396972B2 patent drawing

AI summary

An IC assembly includes multiple microelectronic dies embedded in a substrate material using capillary forces such that the contact surface of each microelectronic die is coplanar with a planar upper surface of the substrate material. The substrate material is deposited as a layer of uncured polymer in a paste (or other solid form) on a base chip, and then the microelectronic dies are mounted on the layer surface in a predefined pattern. The uncured polymer is then heated until becomes a flowable liquid, causing the microelectronic dies to be pulled into the liquid polymer by capillary forces until the contact surface of each microelectronic die is coplanar with the upper liquid polymer surface. The liquid polymer is then cured to form the substrate material as a cross-linked robust solid film that fixedly secures the microelectronic dies in the predefined pattern. The microelectronic dies are then interconnected using standard metallization techniques.