Redistribution Package Structure With Planarized Die Interface
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Solution Overview
Problem
The uneven surface topology of the back-side redistribution circuit structure in semiconductor package structures leads to air or void trapping between the semiconductor die and the redistribution circuit, causing undesired movement during thermal processes, reducing reliability and performance, and risking moisture-related issues like 'popcorn' effects during high-temperature tests.
Innovation Solution
An additional planarizing process is applied to the back-side redistribution circuit structure to achieve a smooth outer surface, enhancing the placement of the semiconductor die and improving the package structure's reliability and performance. Additionally, a thermal conduction layer or film is introduced between the semiconductor die and the redistribution circuit to facilitate heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the back-side redistribution circuit structure is used with uneven surface topology, then the manufacturing process is simpler, but air or void trapping occurs between the semiconductor die and the redistribution circuit
Solution Approach 1:
A planarizing process is performed on the back-side redistribution circuit structure before placing the semiconductor die to create a smooth surface. This preliminary action eliminates surface unevenness that would otherwise cause air or void trapping, ensuring reliable die placement while maintaining manufacturing efficiency
Solution Approach 2:
A planarizing layer is introduced as an intermediary between the redistribution circuit structure and the semiconductor die. This layer fills in surface irregularities and provides a flat interface, preventing void formation without requiring complete redesign of the underlying circuit structure
2Reliability
If the planarizing process is applied to achieve a smooth surface, then the placement stability is improved, but the manufacturing complexity increases
Solution Approach 1:
The surface topology parameter of the back-side redistribution circuit structure is changed from uneven to smooth through the planarizing process. This parameter change ensures proper die placement and eliminates void formation, with the added benefit that the planarized surface improves subsequent packaging processability
3Productivity
If the semiconductor die is placed on the uneven surface, then the manufacturing time is reduced, but moisture-related issues like popcorn effects occur during high-temperature tests
Solution Approach 1:
The planarizing process is performed as a preliminary step before die placement to eliminate surface unevenness. This prevents the formation of voids where moisture could be trapped, thereby preventing popcorn effects during high-temperature testing while maintaining efficient manufacturing throughput
Solution Approach 2:
The potential harm of adding a planarizing step is converted into a benefit by demonstrating that this relatively simple process eliminates serious moisture-related reliability failures. The planarization transforms the redistribution circuit surface from a void-prone topology to a reliable, moisture-resistant interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The planarizing process ensures a stable and secure placement of the semiconductor die, reducing the risk of movement and moisture-related issues, while the thermal conduction layer enhances heat dissipation, thereby improving the overall reliability and performance of the package structure.
Implementation Method 1
an additional planarizing process is applied to the back-side redistribution circuit structure to achieve a smooth outer surface
Implementation Method 2
a thermal conduction layer or film is introduced between the semiconductor die and the redistribution circuit to facilitate heat dissipation
Data Source
AI summary
A package structure includes a first redistribution circuit structure, a semiconductor die, a connecting film, and a second redistribution circuit structure. The first redistribution circuit structure includes a dielectric structure and a routing structure disposed therein, where the dielectric structure includes a trench exposing the routing structure. The semiconductor die is disposed on and electrically coupled to the first redistribution circuit structure. The connecting film is disposed in the trench and between the semiconductor die and the first redistribution circuit structure, and the semiconductor die is thermally coupled to the routing structure through the connecting film. The second redistribution circuit structure is disposed on and electrically coupled to the semiconductor die, the second redistribution circuit structure is electrically coupled to the first redistribution circuit structure, and the semiconductor die is disposed between the first redistribution circuit structure and the second redistribution circuit structure.