Planarized Passivation Layer for LCOS Reflectivity
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Solution Overview
Problem
Conventional liquid-crystal-on-silicon (LCOS) devices suffer from non-planar passivation layers, which compromise the reflectivity of the metal layer due to their non-flatness, necessitating the development of planarized passivation layers for optimal performance.
Innovation Solution
A semiconductor device structure featuring a substrate with a dielectric layer, a device layer, and a passivation liner comprising first and second sublayers, where the second sublayer acts as a stop layer for planarization, allowing a fill layer to be deposited and polished to create a substantially planarized top surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional non-planar passivation layers are deposited over the substrate and opening, then the fabrication process is simple, but the reflectivity of the metal layer is compromised
Solution Approach 1:
The passivation layer is divided into multiple sublayers (first sublayer, second sublayer, third sublayer) with different functions. The first sublayer lines the opening for protection, the second sublayer serves as a planarization stop layer, and the third sublayer provides additional passivation. This segmentation allows each sublayer to be optimized for its specific function, achieving planarity while maintaining structural integrity.
Solution Approach 2:
The second sublayer acts as an intermediary stop layer between the fill layer and the underlying structure. This intermediate layer enables controlled planarization by providing a defined stopping point during CMP processing, allowing the fill layer to be planarized without removing the underlying metal layer, thus preserving reflectivity while achieving surface flatness.
2Illumination intensity
If the metal layer is made highly reflective, then optical performance is improved, but the non-planar surface causes light scattering
Solution Approach 1:
The passivation sublayers are deposited and configured in advance before the fill layer planarization process. The first and second sublayers are formed to line the opening and establish a stop layer configuration beforehand, creating a prepared structure that enables subsequent planarization to achieve a flat surface that preserves the underlying metal layer's reflective properties.
Solution Approach 2:
Different sublayers are positioned at different locations with different properties. The first sublayer is concentrated in the opening region for protection, the second sublayer forms a planarization stop layer at the surface level, and the third sublayer provides additional passivation. This local differentiation allows the surface to be planarized while the metal layer beneath maintains its high reflectivity.
3Shape
If planarization is performed without a stop layer, then a flat surface is achieved, but the metal layer is removed or damaged
Solution Approach 1:
The second sublayer serves as a protective intermediary stop layer during the planarization process. This intermediate layer is positioned between the fill layer and the metal layer, allowing CMP to remove excess fill material and planarize the surface while stopping before reaching the metal layer, thus preserving the metal layer's integrity and reflective properties.
Solution Approach 2:
The second sublayer is deposited in advance as a protective cushion layer before the fill layer is added. This pre-positioned stop layer provides a safety buffer that prevents the planarization process from removing the underlying metal layer, ensuring the metal layer's integrity is maintained while still achieving the desired surface flatness.
Data Source
AI summary
A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.