Planarized Solder Pads for Reliable Chip-to-Substrate Bonding
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Solution Overview
Problem
The existing techniques for solder-bonding chips to substrates face reliability issues due to varying pad heights, which limit the size and density of solder pads, as small volumes of solder may not bridge gaps during reflow, resulting in unreliable connections.
Innovation Solution
A method involving forming a dielectric region between pads of different heights, depositing a thick metal layer, planarizing it using CMP to create uniform solder pads, and then depositing a uniform solder layer, ensuring reliable connections with minimal solder usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If small solder bumps are used to reduce solder usage, then cost is reduced, but connection reliability deteriorates due to insufficient solder volume to bridge height gaps
Solution Approach 1:
The patent applies preliminary action by planarizing the pad surfaces before solder bump deposition. This pre-treatment creates uniform pad heights, ensuring that subsequent small solder bumps can reliably bridge the gap without requiring excessive solder volume. The planarization step is performed in advance to eliminate the height variation problem that would otherwise necessitate larger solder bumps.
Solution Approach 2:
The patent changes the physical parameter of pad height through planarization processing. By transforming the pad surface from non-uniform to uniform height, the solder bump volume requirement is reduced while maintaining reliable connections. This parameter change allows the use of smaller solder bumps (reducing solder loss) while preserving connection reliability.
2Reliability
If pad heights are made uniform to improve solder connection reliability, then connection reliability is improved, but manufacturing complexity increases due to additional planarization steps
Solution Approach 1:
The patent employs self-service by integrating the planarization function into the existing manufacturing process flow. The planarization step is incorporated as a standard process stage that automatically levels the pad surfaces, eliminating the need for separate manual intervention or complex additional equipment. This self-contained approach achieves uniform pad heights while minimizing added manufacturing complexity.
3Reliability
If larger solder pads are used to accommodate more solder, then connection reliability is improved, but area utilization deteriorates due to reduced pad density
Solution Approach 1:
The patent changes the height parameter of the pad surface through planarization, creating uniform pad heights. This allows small solder bumps to be used effectively, which in turn allows for smaller pad areas and higher pad density while maintaining reliable connections. The parameter change in surface uniformity enables the use of less solder per connection.
Solution Approach 2:
By performing planarization as a preliminary step, the patent creates optimal conditions for using small solder bumps. This pre-treatment enables high-density pad layouts with reliable connections, as each small solder bump can effectively bridge the standardized height gap without requiring large pad areas.
4Reliability
If more solder is deposited to ensure bridge formation, then connection reliability is improved, but cost increases due to increased solder consumption
Solution Approach 1:
The patent changes the pad surface height parameter through planarization, creating uniform pad heights. This enables the use of small, precisely-controlled solder bumps that consume minimal solder while still forming reliable connections. The parameter change eliminates the need for excessive solder deposition.
Solution Approach 2:
The planarization step is performed in advance to create optimal pad surfaces for small solder bump deposition. This preliminary action ensures that minimal solder volume is required for reliable bridge formation, reducing solder consumption while maintaining connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for small and closely spaced solder pads to form reliable connections with reduced solder usage, enhancing the reliability and cost-effectiveness of solder interconnections.
Implementation Method 1
A chemical-mechanical planarization (CMP) process (or other planarization process) is then performed to planarize the metal layer portions
Implementation Method 2
A uniform layer of solder is then formed over the planarized metal layer, such as by plating, screen printing, or other means
Data Source
Figure 1A~2B
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Figure 8~11
AI summary
A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.