Planarized Wiring Layer Structure for Low-Power Semiconductor Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving miniaturization, low power consumption, high reliability, low off-state current, long data retention, and integration with eye-friendly display technologies using traditional materials and manufacturing methods.
Innovation Solution
The development of a semiconductor device manufacturing method that involves forming a wiring layer with specific insulator and conductor configurations, including the use of oxide semiconductors and advanced processing techniques like chemical mechanical polishing, to create a structure that suppresses oxygen diffusion and enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional manufacturing methods are used for semiconductor devices, then existing processes can be maintained, but miniaturization and performance improvement are limited
Solution Approach 1:
The patent divides the wiring layer into multiple segments with different materials (conductive material, oxide semiconductor material, insulating material) arranged in specific patterns. This segmentation allows each material to perform its optimal function while enabling miniaturization through precise spatial control of each segment
Solution Approach 2:
Different regions of the wiring layer are assigned different material compositions and structures tailored to local functional requirements. For example, oxide semiconductor materials are placed in specific regions to reduce off-state current, while conductive materials are positioned for low resistance pathways, achieving local optimization that enables miniaturization
2Use of energy by moving object
If power consumption is reduced through oxide semiconductor transistors, then energy efficiency improves, but device structure becomes more complex
Solution Approach 1:
The patent merges multiple functions into the wiring layer structure itself. The wiring layer simultaneously serves as electrical connection pathways, oxygen diffusion barriers, and threshold voltage control mechanisms through the integrated use of conductive materials, oxide semiconductor materials, and insulating materials in a unified multi-layer configuration
Solution Approach 2:
The oxide semiconductor material serves multiple functions: it provides low off-state current characteristics for power saving, acts as an oxygen diffusion barrier to protect underlying layers, and enables threshold voltage control through its interaction with adjacent insulating materials. This multi-functionality reduces the need for separate dedicated structures
3Reliability
If oxide semiconductor materials are used to reduce off-state current, then power consumption decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the oxide semiconductor material layer and insulating material layer in a predetermined sequence before final wiring patterning. This preliminary arrangement of functional materials establishes the oxygen diffusion barrier and electrical characteristics early in the process, guiding subsequent manufacturing steps and reducing precision requirements for later operations
Solution Approach 2:
The insulating material acts as an intermediary between the oxide semiconductor material and other wiring layer components. It controls the interaction between oxygen and the oxide semiconductor, enabling reliable off-state current reduction while simplifying the manufacturing process by providing a buffer that reduces precision requirements for material placement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of miniaturized semiconductor devices with low power consumption, high reliability, and low off-state current, while also allowing for data retention and integration with display technologies that prioritize eye-friendliness and transparency.
Implementation Method 1
performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator
Data Source
AI summary
To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.