Planarizing Interlayer Dielectric via Controlled RIE Pressure
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Solution Overview
Problem
The existing methods for planarizing interlayer dielectric (ILD) layers in semiconductor manufacturing, such as using a dual-layer structure with a conformal insulating layer and a spin-on glass (SOG) layer, fail to achieve global planarization, resulting in a convex etching profile and reduced available wafer area due to uneven etching rates across the wafer.
Innovation Solution
A method involving a multilayer structure with a sacrificial layer and an insulating layer, where reaction chamber pressure is controlled to achieve a concave etching profile in the first RIE step, followed by additional RIE steps to completely remove the sacrificial layer and part of the insulating layer, ensuring a planar surface without the need for costly Chemical Mechanical Polishing (CMP) processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional RIE is used for SOG layer etching, then etching process is simple, but available wafer area is reduced due to edge overetching
Solution Approach 1:
The first RIE step performs preliminary selective etching of the SOG layer at higher pressure to create a concave profile that compensates for anticipated edge overetching in subsequent steps. This preliminary action ensures that the final etching results in a planar surface with uniform thickness across the entire wafer, maximizing the available area.
Solution Approach 2:
The process creates a preliminary concave profile that acts as an anti-action to the expected convex overetching at the wafer edges. By pre-forming this compensatory concave shape, the subsequent etching steps naturally result in a planar final surface, preventing edge overetching and preserving wafer area.
2Manufacturing precision
If CMP process is used for ILD planarization, then global planarization is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The mechanical CMP process is replaced with a series of plasma-based RIE processes. The controlled pressure variations in the plasma etching environment create the necessary etching rate differences to achieve global planarization without mechanical polishing, thereby reducing process complexity and cost while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves global planarization, increases the available wafer area, and simplifies the manufacturing process by eliminating conformal characteristics and reducing overetching, thereby saving time and costs.
Implementation Method 1
performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled
Implementation Method 2
performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer
Data Source
AI summary
The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer.