Planarizing Material Layer for Hole Plugging in 3D Transistor Bonding
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Solution Overview
Problem
During the bonding of semiconductor layers in the production of 3-D transistor structures, particles at the bonding interface can lead to hole formation, which complicates the thinning process and exposes underlying oxide layers, potentially causing breakages and contamination, especially in thin FDSOI substrates.
Innovation Solution
A process involving the deposition of a planarizing material layer followed by selective etching to plug holes up to the active zone of the second semiconductor layer, using materials like carbon-based polymers or hydrogen silsesquioxane, which are resistant to HF and can be processed at moderate temperatures, to prevent particle-induced breakages and contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bonding is performed to produce 3-D transistor structures, then productivity is improved, but particles at the bonding interface cause hole formation that worsens manufacturing precision
Solution Approach 1:
The patent applies preliminary action by depositing a planarizing material layer on the second dielectric layer before bonding occurs. This pre-deposition ensures that any holes formed during bonding are already filled, preventing particle-induced defects from propagating through subsequent processing steps. The planarizing material is deposited at moderate temperatures compatible with FDSOI substrates, and its selective etching properties allow it to be removed later without damaging the semiconductor structure.
Solution Approach 2:
The planarizing material layer acts as an intermediary substance between the bonding interface and the semiconductor layers. It temporarily occupies the space where particles might cause damage, and its selective etchability allows it to serve as a sacrificial plug that protects the underlying structure during processing. This intermediary material resolves the contradiction by enabling bonding to proceed while preventing the harmful effects of interface particles.
2Productivity
If thinning is performed to remove bulk silicon, then productivity is improved, but hole formation exposes oxide layers causing breakages that worsens reliability
Solution Approach 1:
The patent implements beforehand cushioning by placing the planarizing material layer in advance at the bonding interface, creating a protective cushion that prevents particles from causing holes that would expose vulnerable oxide layers during thinning. This pre-positioned material absorbs the potential damage from particle contamination, allowing aggressive thinning processes to proceed without compromising the reliability of the oxide layers and semiconductor structure.
3Manufacturing precision
If chemical-mechanical polishing is used for planarization, then manufacturing precision is improved, but it cannot plug holes larger than 100 microns that worsens device complexity
Solution Approach 1:
The patent changes the parameter of planarization from mechanical polishing to chemical deposition and selective etching. The planarizing material is deposited conformally to fill holes of any size, and then selectively etched to plug them. This chemical approach replaces the mechanical CMP process, enabling effective hole plugging for holes larger than 100 microns that would be impossible with polishing alone, while maintaining surface planarity needed for subsequent processing.
4Ease of manufacture
If deposited oxide is used instead of thermal oxide, then ease of manufacture is improved, but resistance to HF is reduced causing faster consumption that worsens reliability
Solution Approach 1:
The patent applies local quality by using deposited oxide specifically for the bonding interface and encapsulation layers where ease of manufacture and planarity are critical, while the underlying thermal oxide layers maintain their superior HF resistance for structural integrity. The planarizing material layer is locally applied at the bonding interface to compensate for the reduced HF resistance of deposited oxide, allowing the system to benefit from both material types in their optimal locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents hole formation and subsequent breakages, allowing for the safe thinning of semiconductor layers and maintaining the integrity of the transistor structure, while avoiding the limitations of chemical-mechanical polishing and reducing the risk of contamination from metal layers.
Implementation Method 1
selectively etching said planarizing material layer, to said second semiconductor layer
Implementation Method 2
the oxide of the lower oxide layer 107 of the lower level is 'exposed' during the HF-based chemical etches used to remove the BOX
Data Source
AI summary
A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.