Planarizing RDL in Fan-Out Packaging via CMP
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Solution Overview
Problem
The increasing miniaturization of semiconductor dies and the need for more integrated functions lead to challenges in packaging, particularly in fan-in packages where I/O pad density is limited due to pitch constraints, resulting in solder bridges and reduced solder ball packing efficiency.
Innovation Solution
The development of a fan-out package process that involves forming Redistribution Lines (RDLs) and through-vias, followed by planarization using Chemical Mechanical Polish (CMP) to increase I/O pad density and improve packaging efficiency, allowing for the redistribution of I/O pads to a larger area and the use of CMP to achieve a planar surface for reliable attachment and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fan-in package is used with limited die area, then packaging cost is reduced, but I/O pad density is limited due to pitch constraints
Solution Approach 1:
The patent transitions from 2D I/O pad arrangement on the die surface to 3D redistribution through multiple layers of RDLs and via structures. This dimensional change allows I/O pads to be redistributed to a larger effective area while maintaining compact die footprint, thereby increasing I/O pad density without increasing die area.
Solution Approach 2:
The patent implements nested structures with multiple RDL layers stacked vertically, where each layer contains additional I/O pads that are electrically connected to underlying layers through via holes. This nesting approach effectively multiplies the I/O pad capacity within the same die area by utilizing vertical space.
2Quantity of substance
If I/O pad pitch is decreased to increase density, then I/O pad density is improved, but solder bridges may occur
Solution Approach 1:
By redistributing I/O pads across multiple vertical layers through RDL structures, the patent increases the effective spacing between adjacent pads in the horizontal plane. This dimensional separation reduces the risk of solder bridges while maintaining high I/O pad density, as pads on different layers do not interfere with each other's solder balls.
3Quantity of substance
If fan-out package process is used to increase I/O pad density, then I/O pad density is improved, but process complexity increases
Solution Approach 1:
The patent divides the I/O pad redistribution process into discrete, manageable segments: forming RDL layers, creating via holes, depositing conductive materials, and planarizing surfaces. This segmentation of the complex fan-out package process into standardized fabrication steps makes the process more controllable and easier to manufacture despite the increased complexity.
4Ease of manufacture
If non-planar surface is used for attachment, then encapsulation is simplified, but attachment reliability is reduced
Solution Approach 1:
The patent performs planarization of the RDL layer surface before performing the attachment process. This preliminary action creates a flat, uniform surface that ensures reliable bonding and proper alignment of subsequent layers, while the planarized surface also simplifies the encapsulation process by providing a uniform topography for molding compound application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances packaging efficiency by increasing I/O pad density, reducing the risk of solder bridges, and ensuring reliable attachment and encapsulation, thereby improving the yield and reliability of semiconductor packages.
Implementation Method 1
performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer
Data Source
AI summary
A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.