Planarizing Semiconductor Devices After Forming Openings
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Solution Overview
Problem
Conventional planarization processes in semiconductor device manufacturing are inadequate for removing residual slurry particles from small, high aspect-ratio openings, leading to contamination of metal plugs and premature device failure, and require additional steps that increase complexity and cost.
Innovation Solution
The method involves filling openings with conductive material before removing excess dielectric material, eliminating the need for a separate removal step and subsequent wet cleans, which reduces contamination risks and simplifies the manufacturing process by avoiding the need for a bake-out step and minimizing damage to substrate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization is performed before filling openings with metal, then the dielectric layer can be removed, but residual slurry particles remain in high aspect-ratio openings causing contamination
Solution Approach 1:
The patent inverts the conventional sequence by filling openings with conductive material first, then performing planarization to remove excess dielectric. This reversal eliminates the problem of slurry particles remaining in openings, as the openings are already filled with metal that prevents slurry accumulation during planarization.
Solution Approach 2:
The conductive material is deposited into openings before the planarization step, serving as a preliminary action that prevents slurry particle contamination. The metal fill acts as a barrier that stops slurry from entering and remaining in high aspect-ratio openings during the subsequent planarization process.
2Object-affected harmful factors
If wet cleans process is used to remove residual slurry, then contamination can be reduced, but additional process steps and complexity are introduced
Solution Approach 1:
The patent extracts the problematic wet cleans step from the manufacturing process by preventing slurry contamination in the first place through the inverted sequence. By filling openings with metal before planarization, the need for subsequent wet cleaning is eliminated, simplifying the overall process.
Solution Approach 2:
The patent converts the potential harm of slurry contamination into a benefit by using the metal fill as a protective barrier. The conductive material that would normally be a separate step becomes a protective element that prevents slurry from entering openings, thereby eliminating the need for additional cleaning steps.
3Object-affected harmful factors
If multiple process steps are used to ensure cleanliness, then contamination is reduced, but manufacturing time and cost increase
Solution Approach 1:
The patent merges the metal fill step with the planarization sequence, combining what would normally be separate operations into an integrated process flow. The conductive material deposition and planarization are coordinated so that the metal fill serves dual purposes: electrical connection and contamination prevention, reducing overall manufacturing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contamination, enhances yield, and simplifies the manufacturing process by eliminating unnecessary steps, thereby improving the reliability and efficiency of semiconductor device production.
Implementation Method 1
the dielectric material around the openings is removed using chemical-mechanical planarization with a suitable slurry
Implementation Method 2
a wet cleans process, e.g., a piranha etch, can be used to remove residual slurry in the openings
Data Source
AI summary
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.


