Planarizing Semiconductor Surfaces Using Etch-Selective Stop Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for planarizing surfaces and fabricating semiconductor wafers with Group III nitride materials face challenges in achieving precise surface planarity and efficient removal of protruding regions, which can affect the quality and efficiency of semiconductor device fabrication, particularly for high-voltage and high-power applications.
Innovation Solution
A method involving the application of a first layer with a stop layer and subsequent chemical mechanical polishing to create a planarized surface, where the stop layer has a high etch selectivity and is composed of materials like amorphous hydrogenated carbon, and an insulating layer is used to form mesas on the substrate, allowing for precise control of surface planarity and removal of semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planarization methods are used on substrates with protruding regions, then surface planarity can be improved, but material removal efficiency and process time increase significantly
Solution Approach 1:
A stop layer is deposited on the protruding regions before applying the insulating layer. This preliminary action creates a protective barrier that prevents excessive material removal during subsequent planarization processes, allowing for more efficient and less time-consuming removal steps while maintaining the required surface planarity.
Solution Approach 2:
The stop layer acts as an intermediary between the protruding regions and the insulating layer. It mediates the planarization process by providing a controlled interface that enables selective removal of the insulating layer without damaging the underlying protruding regions, thereby improving both precision and efficiency.
2Manufacturing precision
If a stop layer with high etch selectivity is used, then manufacturing precision of the planarized surface is improved, but device complexity increases
Solution Approach 1:
The stop layer is designed with specific material properties (high etch selectivity) that enable precise control during planarization. By changing the material parameter (etch selectivity), the process achieves higher precision without requiring complex multi-step fabrication procedures, as the stop layer naturally protects protruding regions during standard planarization steps.
3Reliability
If the insulating layer thickness is uniformly increased to cover protruding regions, then reliability of device fabrication is improved, but surface planarity deteriorates
Solution Approach 1:
The stop layer is deposited beforehand on the protruding regions to create a protective barrier. This allows the insulating layer to be applied with sufficient thickness for reliability without compromising surface planarity, as the stop layer prevents the insulating layer from adding excessive height to the protruding regions during subsequent planarization.
Solution Approach 2:
The stop layer provides localized protection only where needed (on the protruding regions), allowing the insulating layer thickness to be optimized for reliability in those areas while maintaining overall surface planarity. The local application of the stop layer enables differential treatment of different regions of the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of well-planarized surfaces with reduced height differences, facilitating the fabrication of high-voltage and high-power semiconductor devices by ensuring accurate deposition of metallization structures and improving the surface roughness and bow of semiconductor wafers, thus enhancing device performance and handling during processing.
Implementation Method 1
the stop layer comprises a material having an etch selectivity of greater than 1000 over the material of the first layer
Implementation Method 2
The outermost surface of the first layer may be progressively removed by chemical mechanical polishing
Implementation Method 3
depositing an insulating layer onto a substrate including a mesa
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region including at least one compound semiconductor and a stop layer on an upper surface such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface including the stop layer on the upper surface of the protruding region and an outer surface of the first layer.