Planarizing Silicon Channel Layers Using Two-Stage Polishing
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Solution Overview
Problem
Conventional methods for forming single crystalline silicon channel layers in semiconductor devices result in poor surface roughness and increased crystal defects, limiting the integration density and increasing manufacturing costs due to protrusions on the surface of the silicon layer.
Innovation Solution
A method involving the formation of a sacrificial layer on a single crystalline silicon substrate, followed by a first polishing process to remove a portion of the protrusions and a second polishing process to achieve a substantially planar silicon channel layer with improved surface roughness, using a slurry with specific abrasive and pH levels to control the polishing rate and minimize surface damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If thermal treatment is used to transform amorphous silicon layer into single crystalline silicon layer, then crystal structure is improved, but surface roughness deteriorates due to protrusion formation
Solution Approach 1:
The polishing process is divided into two distinct stages: a first polishing process that removes protrusions while preserving the single crystalline silicon layer, and a second polishing process that achieves final planarization. This segmentation allows each stage to optimize for its specific function, resolving the contradiction between crystal structure preservation and surface flatness.
Solution Approach 2:
The first polishing process is performed as a preliminary action before the second polishing process. By removing protrusions in advance, the subsequent second polishing can focus on achieving high-precision planarization without being hindered by surface irregularities, thus improving both crystal structure stability and surface roughness.
2Manufacturing precision
If conventional polishing is used to remove protrusions, then surface flatness is improved, but crystal defects increase due to excessive material removal
Solution Approach 1:
The first polishing process removes only a partial amount of material - specifically targeting protrusions rather than uniformly removing material across the entire surface. This partial action approach achieves surface flatness while minimizing the total material removal, thereby reducing crystal defects.
Solution Approach 2:
The invention changes the polishing parameters by using a two-stage process with different polishing conditions. The first stage uses parameters optimized for protrusion removal, while the second stage uses parameters optimized for fine planarization. This parameter optimization allows achieving surface flatness with minimal crystal damage.
3Reliability
If single crystalline silicon layer thickness is maintained, then transistor performance is improved, but surface protrusions cause patterning issues
Solution Approach 1:
The invention addresses the surface protrusion problem by operating in the vertical dimension through selective polishing, rather than reducing the overall layer thickness in the horizontal dimension. This allows maintaining the required silicon layer thickness for transistor performance while removing only the protruding portions that cause patterning issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in silicon channel layers with reduced crystal defects and improved surface roughness, enabling the formation of transistors with enhanced performance and allowing for higher integration density without significant thickness reduction of the silicon layer, thus reducing manufacturing costs.
Implementation Method 1
A portion of the sacrificial layer and a portion of the protrusion of the single crystalline silicon layer is removed in a first polishing process to define a sacrificial layer pattern and a remaining portion of the protrusion
Implementation Method 2
The surface of the second single crystalline silicon layer is planarized in a second polishing process to remove the remaining portion of the protrusion and define a substantially planar silicon channel layer
Data Source
AI summary
A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.