Plane-less Voltage Reference Interconnects for EMI Shielding
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Solution Overview
Problem
Conventional electronic packaging designs face challenges in minimizing electromagnetic interference and signal crosstalk due to the close proximity of electrical signals and circuit power planes, leading to increased costs and complexity with the need for multiple reference layers.
Innovation Solution
The implementation of a plane-less voltage referencing method that uses stacked interconnect layers with conductive planes and dielectric material to create vertical interconnects, providing electromagnetic shielding and reducing the number of required reference layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional electronic packaging designs use multiple reference layers to minimize electromagnetic interference, then electromagnetic shielding is improved, but device thickness and design complexity increase
Solution Approach 1:
The patent extracts the reference layer from the traditional multi-layer structure and replaces it with an external reference voltage source connected through via holes. This removes the need for dedicated reference layers within the PCB stack-up, reducing device thickness while maintaining electromagnetic shielding effectiveness through the plane-less voltage referencing technique.
Solution Approach 2:
The conductive planes in the patent serve multiple functions: they provide power distribution, signal routing, and electromagnetic shielding simultaneously. By using the same conductive planes for multiple purposes and referencing them to an external voltage source, the design eliminates the need for separate reference layers, thereby reducing thickness without compromising shielding performance.
2Object-affected harmful factors
If conventional designs use multiple reference layers for electromagnetic shielding, then noise reduction is improved, but design complexity increases
Solution Approach 1:
The reference voltage functionality is extracted from the internal PCB layers and moved to an external source. This simplifies the PCB design by removing the complexity of designing and managing multiple reference layers, while the external reference source maintains noise reduction capabilities through the plane-less voltage referencing approach.
Solution Approach 2:
The conductive planes perform multiple functions including power delivery, signal routing, and electromagnetic noise shielding. By making the planes multi-functional and referencing them externally, the design reduces overall complexity while maintaining noise reduction performance, as the same structures serve multiple purposes without requiring additional dedicated reference layers.
3Volume of moving object
If electrical signals are positioned closer together to reduce device size, then device compactness is improved, but signal crosstalk increases
Solution Approach 1:
The patent introduces an external reference voltage source as an intermediary that provides a common reference for all conductive planes. This mediator enables signals to be positioned closer together by providing stable voltage referencing that reduces susceptibility to crosstalk, allowing compact device design while maintaining signal integrity through the plane-less voltage referencing technique.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electromagnetic noise shielding, reduces the thickness of electronic devices, and simplifies the design by minimizing loop-inductance and the need for additional routing layers, resulting in more robust and compact electronic circuit designs.
Implementation Method 1
a first vertical interconnect portion and dielectric material isolating the first vertical interconnect portion from the first conductive plane
Implementation Method 2
The implementation of a plane-less voltage referencing method that uses stacked interconnect layers with conductive planes and dielectric material to create vertical interconnects, providing electromagnetic shielding
Data Source
AI summary
An electronic device comprises an integrated circuit (IC) die including a first plurality of contact pads; and a plurality of stacked interconnect layers. The plurality of stacked interconnect layer include a first interconnect layer including a first conductive plane, a first vertical interconnect portion, and dielectric material isolating the first vertical interconnect portion from the first conductive plane; and a second interconnect layer including a second conductive plane contacting the first conductive plane, a second vertical interconnect portion contacting the first vertical interconnect portion, and the dielectric material isolating the second vertical interconnect portion from the second conductive plane; wherein the first and second vertical interconnect portions are included in a first vertical interconnect through the first and second conductive planes that contacts a first contact pad of the first plurality of contact pads.