Plane Skew Methodology for Flash Memory Peak Current Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current flash memory designs face challenges in reducing peak current consumption (peak ICC), which can lead to power drop and malfunctions, especially when multiple flash memories are operated concurrently.
Innovation Solution
The implementation of a plane skew methodology, where the control circuit determines the position of a program loop in a sequence and initiates inhibit bit line ramping events with a ramping start time delay for subsequent planes, staggering the ramping of bit lines to reduce peak ICC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple planes perform program loops simultaneously, then programming productivity is improved, but peak current consumption increases causing power drop and malfunctions
Solution Approach 1:
The patent applies periodic action by implementing staggered program loops across multiple planes. Instead of all planes executing program loops simultaneously, planes are assigned different time offsets (e.g., plane 0 starts at time T, plane 1 starts at time T+Δt, plane 2 starts at time T+2Δt). This periodic staggering distributes the peak current consumption events across different time periods, preventing simultaneous current peaks while maintaining overall programming productivity.
2Ease of operation
If inhibit bit line ramping is performed simultaneously across all planes, then operation simplicity is maintained, but peak current consumption is exacerbated
Solution Approach 1:
The patent applies segmentation by dividing the simultaneous inhibit bit line ramping operation into separate, staggered operations for each plane. The control circuit generates different time offsets for each plane's inhibit bit line ramping, so that plane 0's inhibit ramping occurs at time T1, plane 1's occurs at time T1+Δt, and so on. This segments the current consumption events across time, reducing peak current while maintaining systematic control through automated time offset management.
Data Source
AI summary
An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.